ICS87972I Datasheet, PDF (12/17 Pages) Integrated Circuit Systems – LOW SKEW, 1-TO-12 LVCMOS CLOCK MULTIPLIER/ZERO DELAY BUFFER

ICS87972I
LOW SKEW, 1-TO-12
LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
APPLICATION SCHEMATIC EXAMPLE
Figure 4 shows an application schematic example of
ICS87972I. This example provides general handling of input/
output termination, logic control input and power supply filter-
ing. In this example, the clock inputs are driven by LVCMOS
drivers. Series termination for LVCMOS drivers is shown. Ad-
ditional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. The logic control in-
put can be either hardwired on the board or controlled by
LVCMOS drivers. In this example, both hardwired and
LVCMOS driver controlling the logic input are shown. For the
power supply pins, it is recommended at least one decoupling
capacitor per power pin. The decoupling capacitors should
be placed as close to the power pins as possible.
R9 33
Ro=16 Ohm
LVCMOS
R10 33
Ro=16 Ohm
LVCMOS
R11 33
Ro=16 Ohm
LVCMOS
R12 33
Ro=16 Ohm
LVCMOS
R7
VDD
10 - 15
Zo = 50
Zo = 50
VDD
R8
1K
Zo = 50
Zo = 50
R5
1K
C16
10u
C11
0. 01u
U1
1
2
3
4
5
GNDI
nMR/OE
FRZ_CLK
FRZ_DATA
6 ^FSEL_FB2
7
8
9
PLL_SEL
REF_SEL
CLK_SEL
10 ^CLK0
11
12
13
CLK1
XTAL1
XTAL2
VDDA
87972i
R1
43
VDDO
Zo = 50
39
GNDO
QB0
VDDO
QB1
38
37
36
35
GNDO ₃₄
QB2
VDDO
QB3
33
32
31
EXT_FB ₃₀
GNDO
QFB
VDD
FSEL_FB0
29
28
27
VDD
R2 43
VDD
R2 43
C5
0. 1uF
Zo = 50
Zo = 50
R13 1K
LVCMOS
R14 1K
R3 43
LVCMOS
(U1-17)
(U1-22)
VDDO
(U1-33)
(U1-37)
(U1-45) (U1-49)
VDD=3.3V
VDDO=3.3V
C3
0. 1uF
C4
0.1uF
C6
0. 1uF
C7
0.1uF
C8
0.1uF
C9
0.1uF
Zo = 50
Logic Input Pin Examples
Set Logic
VDD _{Input to}
'1'
RU1
1K
To Logic
Input
pins
RD1
Not Install
Set Logic
VDD _{Input to}
'0'
RU2
Not Install
To Logic
Input
pins
RD2
1K
FIGURE 4. ICS87972I LAYOUT SCHEMATIC
87972DYI
www.idt.com
12
REV. E JUNE 25, 2010