ICS8714004I Datasheet, PDF (8/31 Pages) Integrated Device Technology – Output frequency range

ICS8714004I Data Sheet
FemtoCLock^® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
AC Electrical Characteristics
Table 5A. PCI Express Jitter Specifications, V_CC = V_CCO = 3.3V ± 5% or 2.5V ± 5%, V_EE = 0V, T_A = -40°C to 85°C
Symbol
Parameter
Test Conditions
PCIe Industry
Minimum Typical Maximum Specification
t_j
(PCIe Gen 1)
Phase Jitter
Peak-to-Peak;
NOTE 1, 4
ƒ= 100MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 125MHz,
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
20
30
86
12
25
86
t_{REFCLK_HF_RMS} Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
ƒ= 100MHz
High Band: 1.5MHz - Nyquist
(clock frequency/2)
ƒ= 125MHz
High Band: 1.5MHz - Nyquist
(clock frequency/2)
2
3
3.1
0.8
1.4
3.1
t_{REFCLK_LF_RMS} Phase Jitter RMS;
(PCIe Gen 2) NOTE 2, 4
ƒ= 100MHz
Low Band: 10kHz - 1.5MHz
ƒ= 125MHz
Low Band: 10kHz - 1.5MHz
0.1
0.4
3.0
0.1
0.4
3.0
t_{REFCLK_RMS}
(PCIe Gen 3)
Phase Jitter RMS;
NOTE 3, 4
ƒ= 100MHz
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
ƒ= 125MHz
Evaluation Band: 0Hz - Nyquist
(clock frequency/2)
0.5
0.7
0.8
0.2
0.4
0.8
Units
ps
ps
ps
ps
ps
ps
ps
ps
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions. For additional information, refer to the PCI Express Application Note section in the datasheet.
NOTE 1: Peak-to-Peak jitter after applying system transfer function for the Common Clock Architecture. Maximum limit for PCI Express Gen 1
is 86ps peak-to-peak for a sample size of 10⁶ clock periods.
NOTE 2: RMS jitter after applying the two evaluation bands to the two transfer functions defined in the Common Clock Architecture and
reporting the worst case results for each evaluation band. Maximum limit for PCI Express Generation 2 is 3.1ps RMS for t_{REFCLK_HF_RMS}
(High Band) and 3.0ps RMS for t_{REFCLK_LF_RMS} (Low Band).
NOTE 3: RMS jitter after applying system transfer function for the common clock architecture. This specification is based on the PCI Express
Base Specification Revision 0.7, October 2009 and is subject to change pending the final release version of the specification.
NOTE 4: This parameter is guaranteed by characterization. Not tested in production.
ICS8714004DKI REVISION A MARCH 24, 2014
8
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