ICS8714004I Datasheet, PDF (25/31 Pages) Integrated Device Technology – Output frequency range

ICS8714004I Data Sheet
FemtoCLock^® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
Logic Control Input E xamples
Set Logi c
Set Logi c
VDD _{Input to '1'} VDD _{Input to '0'}
RU1
1K
To L ogic
In put
pins
RD1
Not Ins tall
RU2
Not Install
To L ogic
In put
pins
RD2
1K
V DD
C2
10uF
FB2
VDDA 2
1
C3
10uF
BL M1 8B B22 1S N1
3.3V
FB1
2
1
BLM18B B221SN1
C1
0.1uF
U1
OE_ MLV DS
OE0
OE1
2
8 OE_MLVDS
9 OE0
OE 1
MR
P LL_SEL
F BI_DIV0
F BI_DIV1
F BO_DIV
PDI V0
PDI V1
QDIV0
QDIV1
QDIV2
QDIV3
7
5 MR
P LL _SE L
12
13 F BI_DIV0
6 F BI_DIV1
F BO_DIV
39
40 PDIV0
P DIV1
17
18 QDIV0
19 QDIV1
20 QDIV2
QDIV 3
36
VDDA
34
Q0 33
nQ0
32
Q1 31
nQ1
VDD
C4
0. 1uF
C6
C7
0. 1uF 0. 1uF
C8
0. 1uF
C9
0.1uF
C10
0.1uF
C11
0.1uF
V DDA
C5
0. 1uF
R6 33
R9 33
R7
50
Place each 0.1uF bypass cap directly
adjacent to its corresponding VDD or
VDDA pin.
1" t o 14 "
Zo = 50
0. 5" t o 3. 5"
Zo = 50
+
Zo = 50
R4
50
Zo = 50
-
HCSL_Receiv er
PCI E xpress Add-In Card
To MLVDS bus
MLV DS
nMLVDS
3
MLVDS
4
nMLV DS
OE_MLVDS = 1
to select
MLVDS output
Zo = 50 Ohm
CLK 37
R1
CLK
Zo = 50 Ohm 100 nCLK 38
nCLK
LVDS Driv er
R13
49.9
R12
49.9
15
F BIN
14
nFBIN
29
Q2 28
nQ2
HCS L Terminati on
26
Q3 ₂₅
nQ3
21
IREF
R3 33
R2 33
Optional
R11
475
0" t o 18 "
Zo = 50
Zo = 50
R8
50
24
FBOUT
23
nFBOUT
+
-
HCSL_Rec ei v er
R5
50 _{PCI E xpress}
Point-to-Point
Connecti on
Figure 7. ICS8714004I Schematic Example
ICS8714004DKI REVISION A MARCH 24, 2014
25
©2014 Integrated Device Technology, Inc.