ICS8714004I Datasheet, PDF (16/31 Pages) Integrated Device Technology – Output frequency range

ICS8714004I Data Sheet
FemtoCLock^® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
floating (FBO_DIV and FBI_DIV1:0). QDIV0 needs to be ÷4, which
is a default value so this pin can be left floating. QDIV1 must be HIGH
for ÷5, so this pin must be pulled high or driven high externally.
OE[1:0] = 01, so OE0 can Float and OE1 must be pulled Low.
25 MHz
MLVDS
MLVDS
Master Clock Card
ICS8714004I
÷4
CLK
CLK
100 MHz HCSL
SSC Synthesizer
ICS841402I
FemtoClock
VCO
100 MHz HCSL
FPGA
125 MHz HCSL
PCIe Serdes
Backplane
25 MHz
MLVDS
Slave Clock Card
Slave synthesizer
Off or output disabled
ICS8714004I
÷4
CLK
CLK
SSC Synthesizer
ICS841402I
FemtoClock
VCO
100 MHz HCSL
FPGA
125 MHz HCSL
PCIe Serdes
Figure 1, Example Backplane Application
Bold lines
indicate active clock path
This example shows a case where each card may be dynamically
configured as a master or slave card, hence the need for an
ICS8714004I and ICS841402I on each card. On the master timing
card, the ICS841402I provides a 100MHz reference to the
ICS8714004I CLK, nCLK input. The M-LVDS pair on the
ICS8714004I is configured as an output (OE_MLVDS = Logic 1) and
the internal divider is set to ÷4 to generate 25MHz M-LVDS to the
backplane. The 25MHz clock is also used as a reference to the
FemtoClock PLL which multiplies to a VCO frequency of 500MHz.
Each of the four output pairs may be individually set for ÷4 or ÷5 for
125MHz or 100MHz operation respectively and in this example, one
output pair is set to 100MHz for the FPGA and another output pair is
set to 125MHz for the PCI Express serdes. For the slave card, the
M-LVDS pair is configured as an input (OE_MLVDS = LOW) and the
FemtoClock PLL multiplies this reference frequency to 500MHz VCO
frequency and the output dividers are set to provide 100MHz to the
FPGA and 125MHz to the PCI Express Serdes as shown.
ICS8714004DKI REVISION A MARCH 24, 2014
16
©2014 Integrated Device Technology, Inc.