ICS8714004I Datasheet, PDF (2/31 Pages) Integrated Device Technology – Output frequency range

ICS8714004I Data Sheet
Block Diagram
FemtoCLock^® Zero Delay Buffer/Clock Generator for PCI Express™ and Ethernet
PDIV1
PDIV0
Pulldown
Pulldown
CLK
nCLK
Pulldown
Pullup/Pulldown
PDIV1:0
00 ÷4 (default)
01 ÷5
10 ÷8
11 ÷1
OE_MLVDS ^Pullup
MLVDS
nMLVDS
FBI_DIV1 ^Pullup
FBI_DIV0 ^Pullup
FBIN
nFBIN
Pulldown
Pullup/Pulldown
IREF
FBI_DIV1:0
00 ÷1
01 ÷2
10 ÷4
11 ÷5 (default)
PLL_SEL ^Pullup
0
PLL
PD
VCO Range
1
490-660MHz
MR ^Pulldown
Pull-up resistor (PU) on pin (power-up default is HIGH if not externally driven)
Pull-down resistor (PD) on pin (power-up default is LOW if not externally driven)
QDIV0
0 ÷4 (default)
1 ÷5
QDIV1
0 ÷4 (default)
1 ÷5
QDIV2
0 ÷4 (default)
1 ÷5
QDIV3
0 ÷4 (default)
1 ÷5
FBO_DIV
0 ÷4 (default)
1 ÷5
2
OE[1:0] (PU, PU)
QDIV0 (PD)
Q0
nQ0
QDIV1 (PD)
Q1
nQ1
QDIV2 (PD)
Q2
nQ2
QDIV3 (PD)
Q3
nQ3
FBO_DIV (PD)
FBOUT
nFBOUT
ICS8714004DKI REVISION A MARCH 24, 2014
2
©2014 Integrated Device Technology, Inc.