ICS841664I Datasheet, PDF (8/16 Pages) Integrated Device Technology – FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR

ICS841664I
FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
APPLICATION INFORMATION
PRELIMINARY
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. To achieve optimum jitter per-
formance, power supply isolation is required. The ICS841664I
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. V V V and
DD, DDA, DDOA
V_DDOB should be individually connected to the power supply plane
through vias, and 0.01µF bypass capacitors should be used for
each pin. Figure 1 illustrates this for a generic V pin and also
DD
shows that V_DDA requires that an additional10Ω resistor along
with a 10µF bypass capacitor be connected to the V_DDA pin.
3.3V
V_DD
.01μF 10Ω
V_DDA
.01μF
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS841664I has been characterized with 18pF parallel
resonant crystals. The capacitor values shown in Figure 2 below
were determined using a 25MHz, 18pF parallel resonant crystal
and were chosen to minimize the ppm error.
X1
18pF Parallel Crystal
XTAL_OUT
C1
27p
XTAL_IN
C2
27p
FIGURE 2. CRYSTAL INPUt INTERFACE
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
8
ICS841664AGI REV. A JANUARY 30, 2009