ICS841664I Datasheet, PDF (5/16 Pages) Integrated Device Technology – FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR

ICS841664I
FEMTOCLOCK™ CRYSTAL-TO-HCSL CLOCK GENERATOR
PRELIMINARY
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Mode of Oscillation
Frequency
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
NOTE: Characterized using an 18pF parallel resonant crystal.
Minimum Typical Maximum
Fundamental
25
50
7
0.1
Units
MHz
Ω
pF
mW
TABLE 6A. LVCMOS AC CHARACTERISTICS, V_DD = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
f_MAX
t_R / t_F
odc
Output Frequency REF_OUT
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
Minimum
Typical
25
1
50
Maximum
Units
MHz
ns
%
TABLE 6B.
HCSL
AC
CHARACTERISTICS,
V=
DD
V
DDOA
=V
DDOB
= 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
f_MAX
Output Frequency
VCO/5
VCO/4
125
156.25
MHz
MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 1
125MHz,
(1.875MHz - 20MHz)
156.25MHz,
(1.875MHz - 20MHz)
0.35
ps
0.35
ps
tsk(o)
Output Skew;
NOTE 2, 3
QAx/nQAx,
QBx/nQBx
ps
t_L
V_HIGH
V_LOW
V_OVS
V_UDS
V_rb
V_CROSS
ΔV_CROSS
PLL Lock Time
Voltage High
Voltage Low
Max. Voltage, Overshoot
Min. Voltage, Undershoot
Ringback Voltage
Absolute Crossing Voltage
Total Variation of V_CROSS over all
edges
660
700
-150
0.3
-0.3
0.2
250
1
ms
850
mV
150
mV
0.3
V
-0.3
V
V
550
mV
140
mV
t_R / t_F
Output Rise/Fall Time
QAx/nQAx,
QBx/nQBx
measured between
0.175V to 0.525V
350
ps
Δt_R /Δt_F
odc
Rise/Fall Time Variation
Output Duty Cycle
QAx/nQAx,
QBx/nQBx
125
ps
50
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established
when the device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet
specifications after thermal equilibrium has been reached under these conditions.
NOTE: All specifications are taken at 125MHz and 156.25MHz.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT^™ / ICS^™ HCSL CLOCK GENERATOR
5
ICS841664AGI REV. A JANUARY 30, 2009