9DBV0941_17 Datasheet, PDF (8/18 Pages) Integrated Device Technology – 9-Output 1.8V HCSL Fanout Buffer with Zo = 100ohms

9DBV0941 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = T_COM or T_IND; Supply voltages per normal operation conditions; see Test Loads for loading conditions
Parameter
SYMBOL
CONDITIONS
MIN
TYP
Slew Rate
Scope averaging on, fast slew rate setting
1.6
2.6
Trf
Scope averaging on, slow slew rate setting
1.2
2.0
Slew Rate Matching
Voltage High
Voltage Low
Max Voltage
Min Voltage
Vswing
ΔTrf
V_HIGH
V_LOW
Vmax
Vmin
Vswing
Slew rate matching, scope averaging on
Statistical measurement on single-ended signal ₆₆₀
using oscilloscope math function.
(Scope averaging on)
-150
Measurement on single ended signal using
absolute value. (Scope averaging off)
-300
Scope averaging off
300
6
758
43
775
12
1428
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250
391
MAX UNITS NOTES
4.3 V/ns 1,2,3
3.2 V/ns 1,2,3
20
% 1,2,4
850
7
mV
150
7
1150
7
mV
7
mV 1,2
550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
14
140 mV 1,6
1_{Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33Ω for Zo = 50Ω (100Ω differential trace}
2 _{Measured from differential waveform.}
3 _{Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around}
differential 0V.
4 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the}
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 _{Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising edge}
(i.e. Clock rising and Clock# falling).
6 _{The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross absolute)}
allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 _{660mV Vhigh is the minimum when VDDIO is >= 1.05V +/-5%. If VDDIO is < 1.05V +/-5%, the minimum Vhigh will be VDDIOmin -}
250mV. For example, for VDDIO = 0.9V +/-5%, VHIGHmin will be 860mV - 250mV = 610mV.
Electrical Characteristics–Current Consumption
TA = T_COM or T_IND; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
I_DDR
VDDR at 100MHz
Operating Supply Current
I_DDDIG
VDDIG, all outputs at 100MHz
I_DDO
VDDO1.8 + VDDIO, all outputs at 100MHz
Powerdown Current
I_DDRPD
I_DDDIGPD
I_DDOPD
VDDR, CKPWRGD_PD# = 0
VDDDIG, CKPWRGD_PD# = 0
VDDO1.8 + VDDIO, CKPWRGD_PD# = 0
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Input clock stopped.}
3
6
35
0.4
0.6
0.002
MAX
5
10
40
1
1
0.1
UNITS
mA
mA
mA
mA
mA
mA
NOTES
1
1
1
1,2
1, 2
1, 2
9-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO = 100OHMS
8
MARCH 14, 2017