9DBV0941_17 Datasheet, PDF (1/18 Pages) Integrated Device Technology – 9-Output 1.8V HCSL Fanout Buffer with Zo = 100ohms

9-Output 1.8V HCSL Fanout Buffer
with Zo = 100ohms
9DBV0941
DATASHEET
Description
The 9DBV0941 is a member of IDT's Full-Featured PCIe
family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100
transmission lines.
Recommended Application
PCIe Gen1–3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
• 9 1–200MHz Low-Power (LP) HCSL DIF pairs with
ZO = 100
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• Additive cycle-to-cycle jitter < 5ps
• Output-to-output skew < 60ps
• Additive phase jitter is < 100fs rms for PCIe Gen3
• Additive phase jitter < 300fs rms (12kHz-20MHz at
125MHz)
Block Diagram
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
• 100 direct connect; saves 36 resistors and 62mm²
compared to standard HCSL
• 53mW typical power consumption; eliminates thermal
concerns
• Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
• OE# pins; support DIF power management
• HCSL-compatible differential input; can be driven by
common clock sources
• SMBus-selectable features allow optimization to customer
requirements
• Slew rate for each output; allows tuning for various line
lengths
• Differential output amplitude; allows tuning for various
application environments
• 1MHz to 200MHz operating frequency
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Device contains default configuration; SMBus interface not
required for device operation
• 6 x 6 mm 48-VFQFPN; minimal board space
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0941 MARCH 14, 2017
1
©2017 Integrated Device Technology, Inc.