9DBV0941_17 Datasheet, PDF (7/18 Pages) Integrated Device Technology – 9-Output 1.8V HCSL Fanout Buffer with Zo = 100ohms

9DBV0941 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = T_COM or T_IND; Supply voltages per normal operation conditions; see Test Loads for loading conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
1.7
1.8
1.9
V
Output Supply Voltage
VDDIO
Low Voltage Supply LP-HCSL Outputs
0.9975 1.05-1.8 1.9
V
Ambient Operating
T_COM
Commercial range
0
25
70
°C
1
Temperature
T_IND
Industrial range
-40
25
85
°C
1
Input High Voltage
V_IH
Single-ended inputs, except SMBus
0.75 V_DD
V_DD + 0.3 V
Input Mid Voltage
V_IM
Single-ended tri-level inputs ('_tri' suffix)
0.4 V_DD
0.6 V_DD
V
Input Low Voltage
V_IL
Single-ended inputs, except SMBus
-0.3
0.25 V_DD V
I_IN
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
5
µA
Input Current
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
V_IN = VDD; Inputs with internal pull-down resistors
200
µA
Input Frequency
F_in
1
Pin Inductance
L_pin
C_IN
Logic Inputs, except DIF_IN
1.5
Capacitance
C_{INDIF_IN}
DIF_IN differential clock inputs
1.5
C_OUT
Output pin capacitance
Clk Stabilization
T_STAB
From V_DD power-up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
f_MODINPCIe
Allowable frequency for PCIe applications
(Triangular modulation)
30
Input SS Modulation
Frequency non-PCIe
f_MODIN
Allowable frequency for non-PCIe applications
(Triangular modulation)
0
OE# Latency
t_LATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
1
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
t_F
Fall time of single-ended control inputs
Trise
t_R
Rise time of single-ended control inputs
SMBus Input Low Voltage V_ILSMB
V_DDSMB = 3.3V, see note 4 for V_DDSMB < 3.3V
SMBus Input High Voltage V_IHSMB
V_DDSMB = 3.3V, see note 5 for V_DDSMB < 3.3V
2.1
SMBus Output Low Voltage V_OLSMB
at I_PULLUP
SMBus Sink Current
I_PULLUP
at V_OL
4
Nominal Bus Voltage
V_DDSMB
Bus voltage
1.7
SCLK/SDATA Rise Time
t_RSMB
(Max VIL - 0.15V) to (Min VIH + 0.15V)
SCLK/SDATA Fall Time
t_FSMB
(Min VIH + 0.15V) to (Max VIL - 0.15V)
SMBus Operating
Frequency
f_MAXSMB
Maximum SMBus operating frequency
1 _{Guaranteed by design and characterization, not 100% tested in production.}
2 _{Control input must be monotonic from 20% to 80% of input swing.}
3 _{Time from deassertion until outputs are > 200 mV.}
4 _{For VDDSMB < 3.3V, VILSMB < = 0.35VDDSMB.}
5 _{For VDDSMB < 3.3V, VIHSMB > = 0.65VDDSMB.}
6 _{DIF_IN input.}
7 _{The differential input clock must be running for the SMBus to be active.}
200
MHz
2
7
nH
1
5
pF
1
2.7
pF
1,6
6
pF
1
1
ms
1,2
33
kHz
66
kHz
3
clocks 1,3
300
µs
1,3
5
ns
2
5
ns
2
0.8
V
4
3.3
V
5
0.4
V
mA
3.6
V
1000
ns
1
300
ns
1
400
kHz
7
MARCH 14, 2017
7
9-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO = 100OHMS