9DBV0941_17 Datasheet, PDF (17/18 Pages) Integrated Device Technology – 9-Output 1.8V HCSL Fanout Buffer with Zo = 100ohms

9DBV0941 DATASHEET
Ordering Information
Part / Order Number
9DBV0941AKLF
9DBV0941AKLFT
9DBV0941AKILF
9DBV0941AKILFT
Shipping Packaging
Trays
Tape and Reel
Trays
Tape and Reel
Package
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
48-pin VFQFPN
Temperature
0 to +70° C
0 to +70° C
-40 to +85° C
-40 to +85° C
“LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant.
“A” is the device revision designator (will not correlate with the datasheet revision).
Revision History
Rev. Initiator Issue Date Description
1. Updated front page text.
2. Updated block diagram.
3. Updated electrical tables.
4. Updated test loads diagrams.
5. Updated Smbus byte 2, 3 and 6 labeling. Functionality did not
A
RDW 8/27/2014 change.
6. Updated min Vhigh on DIF outputs from 630mV to 660mV, correcting
a typo.
7. Corrected Conditions for Slew Rate in DIF Low-Power HCSL Outputs.
8. Added additive phase jitter image.
9. Move to final.
B
RDW
8/28/2014
1. Corrected Supply Voltage in Absolute Maximum Ratings.
2. Lowered additive phase jitter specs.
1. Revised front page text extensively.
2. Added note about Spread Spectrum Compatibility to the features.
3. Change pin name of VDDA1.8 to VDD1.8 and GNDA to GND to clarify
that this part does not have a PLL. This is a document change only.
There is no silicon change.
4. Corrected OE8# to indicate an internal pull down, not a pull up.
5. Added epad nomenclature to DS
C
RDW 3/28/2016 ^{6. Updated package drawing to latest version - no package change.}
7. Added reference to AN-891.
8. Updated "Current Consumption" table to remove references to
VDDA1.8
9. Added "RMS additive phase jitter: 251fs" to phase noise plot
10. Updated "Clock Input Parameters" table for consistency - no silicon
change.
11. Updated "Output Duty Cycle, Jitter, Skew and PLL Characteristics"
and "Phase Jitter" tables to remove references to bypass mode.
1. Removed "...bypass mode." reference in note 3 under Output Duty
Cycle table.
D
RDW
3/14/2017
2. Corrected spelling errors/typos.
3. Change VDDA to VDDO1.8 in Current Consumption table.
4. Update Additive Phase Jitter conditions for PCIe Gen3.
5. Updated package outline drawings.
Page #
Various
Various
1-5,7-9 14
8,9,15,16
MARCH 14, 2017
17
9-OUTPUT 1.8V HCSL FANOUT BUFFER WITH ZO = 100OHMS