92HD66B Datasheet, PDF (77/286 Pages) Integrated Device Technology – FOUR CHANNEL HD AUDIO CODECS

92HD66B
FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
6.7.26. AFG (NID = 01h): VSPwrState
Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8)
Set
Get
FD800h
Byte 1 (Bits 7:0)
7D8h
Field Name
Rsvd
D5
D4
Bits
R/W
Default
Reset
31:2
R
00000000h
N/A (Hard-coded)
Reserved.
1
RW
0h
POR - ELR
Vendor specific D5 power state, only entered once the part is already in D3cold
(this bit must be set before the command to enter D3cold). If set, this bit over-
rides the D4 bit (bit 0). Includes the power savings of D4, but additionally pow-
ers down GPIO pins, the VAG amp, and the HP amps. Exits this power state
via POR or rising edge of Link Reset.
0
RW
0h
POR - ELR
Vendor specific D4 power state, only entered once the part is already in D3cold
(this bit must be set before the command to enter D3cold). If the D5 bit (bit 1)
is set, this bit is overridden. Includes the power savings of D3cold, but addi-
tionally powers down the HDA interface (no responses). Exit this power state
via POR or rising edge of Link Reset.
6.7.27. AFG (NID = 01h): AnaPort
Reg Byte 4 (Bits 31:24) Byte 3 (Bits 23:16) Byte 2 (Bits 15:8)
Set
7EDh
Get
FED00h / FEC00h
Byte 1 (Bits 7:0)
7ECh
Field Name
Rsvd2
MonoPwd
FPwd
Bits
R/W
Default
Reset
31:7
R
0000000h
N/A (Hard-coded)
Reserved.
6
RW
0h
POR
Power down Mono Output. (Available only on 48-pin versions)
5
RW
0h
POR
Power down Port F
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92HD66B