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92HD66B Datasheet, PDF (20/286 Pages) Integrated Device Technology – FOUR CHANNEL HD AUDIO CODECS
92HD66B
FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
still supported this is done by assigning unique non zero Stream IDs to each converter. All capture
devices (ADCs 0 and 1) may be used to create a multi-channel input stream. There are no restric-
tions regarding digital microphones.
The ADC Converters can be associated with a single stream as long the sample rate and the bits per
sample are the same. The assignment of converter to channel is done using the “CnvtrID” widget
and is restricted to even values. The ADC converters will always put out a stereo sample and there-
fore require 2 channels per converter.
The stream will not be generated unless all entries for the targeted converters are set identically, and
the total number of assigned converter channels matches the value in the NmbrChan field. These
are listed the “Multi-Converter Stream Critical Entries.” table.
An example of a 4 Channel Steam with ADC0 supplying channels 0&1 and ADC1 supplying chan-
nels 2 & 3 is shown below. A 4 Channel stream can be created by assigning the same non-zero
stream id “Strm= N” to both ADC0 and ADC1. The sample rates must be set the same and the num-
ber of channels must be set to 4 channels “NmbrChan = 0011”.
ADC1 CnvtrID
ADC0 CnvtrID
(NID = 0x08)
[3:0]
(NID = 0x07)
[3:0]
Ch = 2
Ch=0
Table 9. Example channel mapping
Figure 1. Multi-channel capture
ADC0.CnvrtID.Channel = 0
ADC1.CnvrtID.Channel = 2
Stream ID
Data
Length
ADC0.CnvrtID.Channel = 2
ADC1.CnvrtID.Channel = 0
Stream ID
Data
Length
ADC0
Left Channel
ADC1
Left Channel
ADC0
Right Channel
ADC1
Right Channel
ADC1
Left Channel
ADC0
Left Channel
ADC1
Right Channel
ADC0
Right Channel
BITCLK
SDI
The following figure describes the bus waveform for a 24-bit, 48KHz capture stream with ID set to 1.
Figure 2. Multi-channel timing diagram
0
0
0
1
0
0
1
1
0
0
ADC0
L23
ADC0 ADC0
L0
R23
ADC0 ADC1
R0
L23
ADC1 ADC1
L0
R23
ADC1
R0
STREAM ID
DATA LENGTH
STREAM TAG
LEFT
RIGHT
LEFT
RIGHT
ADC0
ADC1
DATA BLOCK
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