92HD66B Datasheet, PDF (32/286 Pages) Integrated Device Technology – FOUR CHANNEL HD AUDIO CODECS

92HD66B
FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
PC-Beep may be attenuated and distorted when the CODEC is in D3 depending on the load imped-
ance seen by the output amplifier since all ports are in a low power state while in D3. Load imped-
ances of 10K or larger can support full scale outputs but lower impedance loads will distort unless
the output amplitude is reduced. Digital PC_Beep requires a clock to operate and the CODEC will
prevent the system from stopping the bus clock while in D3 by setting the Clock_Stop_OK bit to 0 to
indicate that the part requires a clock.
2.22. Headphone Drivers
The codec implements headphone capable outputs on some ports. The Microsoft Windows Logo
Program allows up to the equivalent of 100ohms in series. However, an output level of +3dBV at the
pin is required to support 300mV at the jack with a 32ohm load and 1V with a 320 ohm load. Micro-
soft allows device and system manufactures to limit output voltages to address EU safety require-
ments. (WLP 3.09 - please refer to the latest Windows Logo Program requirements from Microsoft.)
The 92HD90 codec does not implement power limiting. Power limiting may be implemented through
the use of an external series resistance.
Although 3 Headphone amplifiers are present, only two may be used simultaneously. Headphone
performance will degrade if more than one port is driving a 32 ohm load.
2.23. GPIO
2.23.1. GPIO Pin mapping and shared functions
GPIO
#
0
1
2
3
4
48 pin
package
46
2
4
48
44
40 pin
package
38
2
3
40
Supply
DVDD
DVDD
DVDD
DVDD
DVDD
SPDIF
In
SPDIF
Out
YES
YES
EAPD
GPI/O
VrefOut
DMIC
Pull
Up
YES
IN
YES
CLK
YES
IN
YES
IN
YES
Pull
Down
50K
50K
50K
50K
50K
2.23.2. Digital Microphone/GPIO Selection
2 functions are available on the DMIC_CLK/GPIO1 and the DMIC_0/GPIO2 pins. To determine
which function is enabled, the order of precedence is followed:
1. If GPIOs are not enabled through the AFG, then at reset, the pins are pulled low by an internal
pull-down resistor.
2. If the GPIO 1 is enabled, the 2 DMIC pins become mute (unless programmed for GPIO or SPDIF
use) and pin2 becomes GPIO with an internal pull-down.
3. If GPIO2 is enabled through the AFG, pin 4 (3 on 40-pin package) becomes a GPIO and is
pulled low by an internal pull-down resistor.
4. If the port is enabled as an input, the digital microphone will be used.
5. If the port is not enabled as an input or if the pin is configured as a GPIO, the digital microphone
path will be mute.
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