92HD66B Datasheet, PDF (13/286 Pages) Integrated Device Technology – FOUR CHANNEL HD AUDIO CODECS

92HD66B
FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
When the HD Audio bus is in a low power state (reset asserted and clock stopped) the CODEC will
generate a Power State Change Request when a change in port connectivity is sensed and then
generate an unsolicited response after the HD Audio link has been brought out of a low power state
and the device has been enumerated. Per HDA015-B, this will take less than 10mS.
The following table summarizes the proper resistor tolerances for different analog supply voltages.
.
AVdd Nominal
Voltage (+/- 5%)
Resistor Tolerance Resistor Tolerance
Pull-Up
SENSE_A/B
4.75V or 5.0V
1%
1%
Table 3. Resistor Tolerance
Resistor
39.2K
20.0K
10.0K
5.11K
2.49K
SENSE_A
SENSE_B
PORT A
PORT E
PORT B
Mono
PORT C
SPDIF0/DMIC1
PORT F
SPDIF1/DMIC1
Pull-up to Avreg (X5) Pull-up to Avreg (X5)
Pull-up to AVDD (X3) Pull-up to AVDD (X3)
Table 4. 48 pin Jack Detect
.
Resistor
SENSE_A
39.2K
PORT A
20.0K
PORT B
10.0K
PORT C
5.11K
PORT F
2.49K
Pull-up to Avreg (X5)
Pull-up to AVDD (X3)
Table 5. 40 pin Jack Detect
See reference design for more information on Jack Detect implementation.
2.4. SPDIF Output
Both SPDIF Outputs can operate at 44.1kHz, 48kHz, 88.2kHz, 96kHz and 192KHz as defined in the
Intel High Definition Audio Specification with resolutions up to 24 bits. This insures compatibility with
all consumer audio gear and allows for convenient integration into home theater systems and media
center PCs.
Note: Peak to peak jitter is currently limited to less than 4.5nS (half of the internal master clock cycle)
which does not meet the IEC-60958-3 0.05UI requirement at 192KHz.
The two SPDIF output converters can not be aligned in phase with the DACs. Even when attached
to the same stream, the two SPDIF output converters may be misaligned with respect to their frame
boundaries.
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