92HD66B Datasheet, PDF (33/286 Pages) Integrated Device Technology – FOUR CHANNEL HD AUDIO CODECS

92HD66B
FOUR CHANNEL HD AUDIO CODECS WITH DUAL CAPLESS HEADPHONE AMPLIFIERS
2.23.3. SPDIF_OUT/GPIO/DMIC Selection
3 functions are available on the SPDF0/GPIO3/DMIC1 and SPDF1/GPIO0/DMIC1 pins. To deter-
mine which function is enabled, the order of precedence is followed:
1. Default at power-on is SPDIF_OUT/DMIC1 for pin 48 (40) and SPDIF_OUT/DMIC1 for pin
46(38)
2. If GPIO is enabled for that pin, it overrides the SPDIF_OUT and DMIC functions for that pin.
3. If the GPIO function is not enabled for that pin, then the DMIC or SPDIF_OUT function may be
enabled by setting the pin input or output enable to 1, respectively. (Setting input and output
enable to 1 at the same time will only enable DMIC)
Note: If the pin selected for DMIC1 input is configured as an output or GPIO, the DMIC block will
behave as if silence is present at the input.
GPIO3 Dig0Pin Input
Enable
Enable
0
0
0
1
1
NA
Dig0Pin Output
Enable
Selected by
DMIC1Vol (NID
0x12)
0
NA
1
NA
No
NA
Yes
NA
NA
Function
Unused (input)
SPDIF0 output
Unused (input)
DMIC1 input
GPIO3
Table 18. Dig0Pin (Pin 48/40) Function Selection
GPIO0 Dig1Pin Input
Enable
Enable
0
0
0
1
1
NA
Dig1Pin Output
Enable
Selected by
DMIC1Vol (NID
0x12)
0
NA
1
NA
No
NA
Yes
NA
NA
Function
Unused (input)
SPDIF1 output
Unused (input)
DMIC1 input
GPIO0
Table 19. Dig1Pin (Pin 46/38) Function Selection
2.24. HD Audio ECR 15b support
The codec implements complete support for the HDA015-B specification building on the support
already present in previous products. HDA015-B features supported are:
1. Persistence of many configuration options through bus and function group reset.
2. The ability to support port presence detect in D3 even when the HD Audio bus is in a low power
state (no clock.)
3. Fast resume times from low power states: 1ms D1 to D0, 2ms D2 to D0, 10mS D3 to D0.
4. Notification if persistent register settings have been unexpectedly reset.
5. SPDIF Out active in D3 (required)
6. The ability to notify the driver that a clock is necessary so entering D3 with the clock stopped is
not permissible
33
©2011 INTEGRATED DEVICE TECHNOLOGY, INC.
V 1.0 2/12
92HD66B