ICS932S431A Datasheet, PDF (7/22 Pages) Integrated Device Technology – Low drift PCIe clocks for Non-Transparent Bridging

Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
T_period
CONDITIONS*
see Tperiod min-max values
33.33MHz output nominal
MIN
-100
29.9970
TYP
30
MAX
100
30.0030
Absolute Clock period
T_pabs 33.33MHz output including jitter 29.4970
30.5030
Clock High Time
T_HIGH
1.5V
12
Clock Low Time
T_LOW
1.5V
12
Output Impedance
R_DSP
V_O = V_DD*(0.5)
12
Output High Voltage
V_OH
I_OH = -1 mA
2.4
Output Low Voltage
V_OL
I_OL = 1 mA
Output High Current
I_OH
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
-33
Output Low Current
I_OL
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
30
Edge Rate
t_slewr/f
Rising/Falling edge rate
1
Rise Time
t_r
V_OL = 0.4 V, V_OH = 2.4 V
0.5
Fall Time
t_f
V_OH = 2.4 V, V_OL = 0.4 V
0.5
Duty Cycle
d_t1
V_T = 1.5 V
45
Group Skew
t_skew
V_T = 1.5 V
Jitter, Cycle to cycle
t_jcyc-cyc
V_T = 1.5 V
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, (unless otherwise specified)
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz}
N/A
N/A
55
0.55
-33
38
4
2
2
55
250
500
NOTES
UNITS
ppm 1,2
ns
2
ns
2
ns
1
ns
1
1
V
1
V
1
mA
1
mA
1
mA
1
mA
1
V/ns
1
ns
1
ns
1
%
1
ps
1
ps
1
Electrical Characteristics - USB48MHz
PARAMETER
Long Accuracy
Clock period
SYMBOL
ppm
T_period
CONDITIONS*
see Tperiod min-max values
48.00MHz output nominal
MIN
TYP
0
20.8333 20.83333
MAX
0
20.8333
Absolute Clock period
T_pabs 48.00MHz output including jitter 20.4833
21.1833
Output Impedance
R_DSP
V_O = V_DD*(0.5)
12
Output High Voltage
V_OH
I_OH = -1 mA
2.4
Clock High Time
T_HIGH
1.5V
8.094
Clock Low Time
T_LOW
1.5V
7.694
Output Low Voltage
V_OL
I_OL = 1 mA
Output High Current
I_OH
V _OH @MIN = 1.0 V
V_OH@MAX = 3.135 V
-29
Output Low Current
I_OL
V_OL @ MIN = 1.95 V
V_OL @ MAX = 0.4 V
29
Edge Rate
t_{slewr/f_USB}
Rising/Falling edge rate
1
Rise Time
t_{r_USB}
V_OL = 0.4 V, V_OH = 2.4 V
1
Fall Time
t_{f_USB}
V_OH = 2.4 V, V_OL = 0.4 V
1
Duty Cycle
d_t1
V_T = 1.5 V
45
Group Skew
t_skew
V_T = 1.5 V
Jitter, Cycle to cycle
t_jcyc-cyc
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%
V_T = 1.5 V
1_{Guaranteed by design and characterization, not 100% tested in production.}
2 _{All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REF is at 14.31818MHz}
1426A—11/12/09
55
10.036
9.836
0.55
-33
27
2
2
2
55
250
350
UNITS ^NOTES
ppm 1,2
ns
2
ns
2
Ω
1
V
1
ns
1
ns
1
V
1
mA
1
mA
1
mA
1
mA
1
V/ns
1
ns
1
ns
1
%
1
ps
1
ps
1
7