ICS932S431A Datasheet, PDF (14/22 Pages) Integrated Device Technology – Low drift PCIe clocks for Non-Transparent Bridging

Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
SMBus Table: Byte Count Register
Byte 8
Pin #
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
-
Name
BC7
BC6
BC5
BC4
BC3
BC2
BC1
BC0
Control Function Type
RW
RW
RW
Byte Count Programming RW
b(7:0)
RW
RW
RW
RW
0
1
Writing to this register will
configure how many bytes will
be read back, default is 8
bytes.
(0 to 7)
PWD
0
0
0
0
0
1
1
1
SMBus Table: Device ID Register
Byte 9
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
DID7
DID6
DID5
DID4
DID3
DID2
DID1
DID0
Control Function Type
0
R
-
R
-
R
-
Device ID
(3B hex)
R
-
R
-
R
-
R
-
R
-
1
PWD
-
0
-
0
-
1
-
1
-
1
-
0
-
1
-
1
SMBus Table: M/N Programming & Control Register
Byte 10
Pin #
Name
Control Function Type
Bit 7
Bit 6
-
CPU
M/N_EN
CPU_STOP Control
CPU and SRC
M/N Programming
RW
Enable
Stop non-free running PC _RW
and SRC clocks.
Bit 5
-
RESERVED
Bit 4
-
RESERVED
Bit 3
Bit 2
SRC, PCI
CPU
Set SRC = 96 MHz and
SRC Alternate Frequency (96% of
Nominal)
PCI = 32 MHz
Only active if
RW
Byte 10, bit 2 = 1
CPU Alternate Frequency (96% of Set alternate CPU
Nominal) Only active if latched
frequency is 166 MHz or 333
frequency:
166 MHz to 160 MHz
RW
MHz.
333 MHz to 320 MHz
Bit 1
54
REF1 Drive Strength
1X or 2X
RW
Bit 0
55
REF0 Drive Strength
1X or 2X
RW
0
Disable
Stop
Normal
1
Enable
PWD
0
Run
1
0
0
Alternate
Frequency
0
Normal
Alternate
Frequency
0
See REF Drive Strength
1
Functionality Table
1
1426A—11/12/09
14