ICS932S431A Datasheet, PDF (19/22 Pages) Integrated Device Technology – Low drift PCIe clocks for Non-Transparent Bridging

Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
PD, Power Down
PD is an asynchronous active high input used to shut off all clocks cleanly prior to system power down.
When PD is asserted, all clocks will be driven low before turning off the VCO. All clocks will start without glitches when PD is
de-asserted.
PD
CPU CPU # SRC SRC# PCIF/PCI USB
REF Note
0
Normal Normal Normal Normal 33MHz 48MHz 14.318MHz
1
1 Iref * 2 or Float Iref * 2 Float
Low
Low
Low
1
Float
or Float
Notes:
1. Refer to SMBus Byte 4 for additional information.
PD Assertion
PD should be sampled high by 2 consecutive CPU# rising edges before stopping clocks. All single ended clocks will be held
low on their next high to low transition.
All differential clocks will be held high on the next high to low transition of the complimentary clock. If the control register
determining to drive mode is set to 'tri-state', the differential pair will be stopped in tri-state mode, undriven.
When the drive mode corresponding to the CPU or SRC clock of interest is set to '0' the true clock will be driven high at 2 x
Iref and the complementary clock will be tristated. If the control register is programmed to '1' both clocks will be tristated.
See SMBus Bytes 4 and 5 for additional information.
PD
CPU, 133MHz
CPU#, 133MHz
SRC, 100MHz
SRC#, 100MHz
USB, 48MHz
PCI, 33MHz
REF, 14.31818
1426A—11/12/09
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