ICS932S431A Datasheet, PDF (3/22 Pages) Integrated Device Technology – Low drift PCIe clocks for Non-Transparent Bridging

Integrated
Circuit
Systems, Inc.
ICS932S431A
Datasheet
Pin Description (Continued)
Pin #
29
30
SCLK
SDATA
PIN NAME
31 Vtt_PwrGd#/PD
32 NC
33 IREF
34 GNDA
35 VDDA
36 CPUCLKC3
37 CPUCLKT3
38 VDDCPU
39 CPUCLKC2
40 CPUCLKT2
41 GNDCPU
42 CPUCLKC1
43 CPUCLKT1
44 VDDCPU
45 CPUCLKC0
46 CPUCLKT0
47 VDDCPU
48 FS_A
49 FS_B/TEST_MODE
50 GNDREF
51 X2
52 X1
53 VDDREF
54 REF1
55 REF0
56 FS_C/TEST_SEL
Type
IN
I/O
IN
N/A
OUT
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
IN
PWR
OUT
OUT
IN
Pin Description
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Vtt_PwrGd# is an active low input used to determine when latched inputs are
ready to be sampled. PD is an asynchronous active high input pin used to put the
device into a low power state. The internal clocks, PLLs and the crystal oscillator
are stopped.
No Connection.
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to
establish the appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Ground pin for the CPU outputs
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
True clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time input to
select between Hi-Z and REF/N divider mode while in test mode. Refer to Test
Clarification Table.
Ground pin for the REF outputs.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock.
14.318 MHz reference clock.
3.3V tolerant input for CPU frequency selection. Low voltage threshold inputs,
see input electrical characteristics for Vil_FS and Vih_FS values.
TEST_Sel: 3-level latched input to enable test mode.
Refer to Test Clarification Table
1426A—11/12/09
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