ICS889872 Datasheet, PDF (7/14 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Parameter Measurement Information, continued
PRELIMINARY
V_IN, V_OUT
800mV
(typical)
V_{DIFF_IN}, V_{DIFF_OUT}
1600mV
(typical)
Clock _20%
Outputs
80%
t_R
Single-Ended & Differential Input Voltage Swing
Output Rise/Fall Time
80%
t_F
V_OD
20%
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V_DD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock
swing is only 2.5V and V_DD = 3.3V, V_REF should be 1.25V and
R2/R1 = 0.609.
Single Ended Clock Input
VDD
R1
1K
IN
V_REF
C1
0.1u
nIN
R2
1K
Figure 2. Single-Ended Signal Driving Differential Input
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
7
ICS889872AK REV. A AUGUST 22, 2007