ICS889872 Datasheet, PDF (1/14 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

PRELIMINARY
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER
W/INTERNAL TERMINATION
ICS889872
General Description
The ICS889872 is a high speed Differential-to-
ICS
LVDS Buffer/Divider w/Internal Termination and is a
HiPerClockS™ _{member of the HiPerClockS™family of high}
performance clock solutions from IDT. The
ICS889872 has a selectable ÷2, ÷4, ÷8, ÷16 output
dividers. The clock input has internal termination resistors,
allowing it to interface with several differential signal types while
minimizing the number of required external components. The
device is packaged in a small, 3mm x 3mm VFQFN package,
making it ideal for use on space-constrained boards.
Features
• Three LVDS outputs
• Frequency divide select options: ÷4, ÷6: >2GHz,
÷8, ÷16: >1.6GHz
• IN, nIN input can accept the following differential input levels:
LVPECL, LVDS, CML
• Output frequency: >2GHz
• Cycle-to-cycle jitter: 1ps (typical)
• Total jitter: 10ps (typical)
• Output skew: 7ps (typical), QA/nQA outputs
• Part-to-part skew: 250ps (typical)
• Propagation Delay: 750ps (typical), QA/nQA outputs
• Full 2.5V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
Block Diagram
Pin Assignment
nRESET/
nDISABLE
Enable
FF
Enable
MUX
IN
50Ω
V_T
50Ω
nIN
V_{REF_AC}
S1
S0
Decoder
÷2, ÷4,
÷8, ÷16
QA
nQA
QB0
nQB0
QB1
nQB1
16 15 14 13
QB0 1
12 IN
nQB0 2
11 VT
QB1 3
10 VREF_AC
nQB1 4
9 nIN
5 6 78
ICS889872
16-Lead VFQFN
3mm x 3mm x 0.95mm package body
K Package
Top View
The Preliminary Information presented herein represents a product in pre-production. The noted characteristics are based on initial product characterization and/or qualification.
Integrated Device Technology, Incorporated (IDT) reserves the right to change any circuitry or specifications without notice.
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
1
ICS889872AK REV. A AUGUST 22, 2007