ICS889872 Datasheet, PDF (12/14 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Reliability Information
Table 7. θ_JA vs. Air Flow Table for a 16 Lead VFQFN
θ_JA by Velocity
Linear Feet per Minute
0
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
Transistor Count
The transistor count for ICS889872 is: 323
Pin compatible with SY89872U
Package Outline and Package Dimensions
Package Outline - K Suffix for 16 Lead VFQFN
Ind exArea
N
To p View
D
Chamfer 4x
0.6 x 0.6 max
OPTIONAL
S eating Plan e
A1
Anvil
Singula tion
OR
A3 ^L
E 2 _E2
2
(N -1)x e
(R ef.)
N
A
0. 08 C
e
(Ref.)
N &N
Odd
C
D2
2
D2
(Ref.)
N &N
Even
e (Ty p.)
2 _{If N & N}
1 ^{are Even}
2
(N -1)x e
(Re f.)
b
Th er mal
Ba se
Table 8. Package Dimensions
JEDEC Variation: VEED-2/-4
All Dimensions in Millimeters
Symbol Minimum Maximum
N
16
A
0.80
1.00
A1
0
0.05
A3
0.25 Ref.
b
0.18
0.30
N_D & N_E
D&E
4
3.00 Basic
D2 & E2
1.00
1.80
e
0.50 Basic
L
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
12
ICS889872AK REV. A AUGUST 22, 2007