ICS889872 Datasheet, PDF (2/14 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
PRELIMINARY
Table 1. Pin Descriptions
Number
1, 2
Name
QB0, nQB0
Type
Output
3, 4
QB1, nQB1 Output
5, 6
QA, nQA
Output
Description
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB0/nQB0).
LVDS interface levels.
Differential output pair. Divide by 2, 4, 8, 16. Unused outputs must be
terminated with 100W across the pin (QB1nQB1).
LVDS interface levels.
Differential undivided output pair. LVDS interface levels.
7, 14
8
9
10
11
12
13
15, 16
V_DD
nRESET/
nDISABLE
nIN
V_{REF_AC}
V_T
IN
GND
S1, S0
Power
Input
Input
Output
Input
Input
Power
Input
Pullup
Pullup
Power supply pins.
Output reset and enable/disable pin. When LOW, resets the divider select,
and align Bank A and Bank B edges. In addition, when LOW, Bank A and
Bank B will be disabled. Input threshold is V_DD/2V.
Includes a 37kΩ pullup resistor. LVTTL / LVCMOS interface levels.
Inverting differential LVPECL clock input. RT = 50Ω termination to V_T.
Reference voltage for AC-coupled applications. Equal to V_DD – 1.4V
(approx.). Maximum sink/source current is 0.5mA.
Termination input. Leave pin floating.
Non-inverting LVPECL differential clock input.
RT = 50Ω termination to V_T.
Power supply ground.
Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB.
Input threshold is VDD/2. 37kW pullup resistor.
LVCMOS/LVTTL interface levels.
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
R_PULLUP
Parameter
Input Pullup Resistor
Test Conditions
Minimum
Typical
37
Maximum
Units
kΩ
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
2
ICS889872AK REV. A AUGUST 22, 2007