ICS889872 Datasheet, PDF (3/14 Pages) Integrated Device Technology – DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

ICS889872
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
Function Tables
Table 3A. Control Input Function Table
Input
Outputs
nRESET
QA, QBx
nQA, nQBx
0
Disabled; LOW
Disabled; HIGH
1
Enabled
Enabled
NOTE: After nRESET switches, the clock outputs are disabled or
enabled following a falling input clock edge as shown in Figure 1.
Figure 1. nRESET Timing Diagram
nRESET
IN
nIN
V_IN Swing
nQBx
QBx
QA
nQA
V_DD/2
t_RR
t_PD
V_OUT Swing
PRELIMINARY
Table 3B. Truth Table
Inputs
nRESET/nDISABLE
S1
1
0
1
0
1
1
1
1
0
X
Outputs
S0
Bank A
Bank B
0
Input Clock
Input Clock ÷2
1
Input Clock
Input Clock ÷4
0
Input Clock
Input Clock ÷8
1
Input Clock
Input Clock ÷16
X QA = LOW, nQA = HIGH; NOTE 1 QBx = LOW, nQBx = HIGH; NOTE 2
NOTE 1: On the next negative transition of the input signal.
NOTE 2: Asynchronous reset/disable function.Absolute Maximum Ratings
IDT™ / ICS™ LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION
3
ICS889872AK REV. A AUGUST 22, 2007