ICS87951I-147 Datasheet, PDF (7/15 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TOLVCMOS ZERO DELAY BUFFER

ICS87951I-147
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
TABLE 6B. AC CHARACTERISTICS, V_DDA = V_DDO = 2.5V±5%, TA = 0°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
QA ÷2
200
MHz
f_MAX
Output Frequency
Qx ÷4
QB, QC, QD ÷8
120
MHz
60
MHz
f_VCO
t(Ø)
tsk(o)
tjit(cc)
t_LOCK
t_R / t_F
odc
PLL VCO Lock Range
Static Phase Offset; ^CLK0
NOTE 1,3
CLK1,
nCLK1
Output Skew; NOTE 2, 3
Cycle-to-Cycle Jitter, RMS;
NOTE 3
PLL Lock Time; NOTE 3
Output Rise/Fall Time
Output Duty Cycle
FVCO ≤ 400MHz,
All Outputs @ same frequency
20% to 80%
250
-180
-500
300
46
500
220
-165
310
9
10
700
54
MHz
ps
ps
ps
ps
mS
ps
%
t_PZL
Output Enable Time
6
ns
t , t Output Disable Time
PLZ PHZ
7
ns
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
IDT^™ / ICS^™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
7
ICS87951I-147 REV A JUNE 21, 2006