ICS87951I-147 Datasheet, PDF (6/15 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TOLVCMOS ZERO DELAY BUFFER

ICS87951I-147
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
TABLE 4D. DC CHARACTERISTICS, V_DDA = V_DDO = 2.5V±5%, TA = 0°C TO 85°C
Symbol
V_IH
V_IL
Parameter
Input High Voltage
Input Low Voltage
DIV_SELA:DIV_SELD,
EXT_FB, MR/nOE,
PLL_SEL, CLK_SEL
DIV_SELA:DIV_SELD,
EXT_FB, MR/nOE,
PLL_SEL, CLK_SEL
CLK0
Test Conditions
I
IN
V_PP
V_CMR
Input Current
Peak-to-Peak
Input Voltage
Common Mode
Input Voltage;
NOTE 1, 2
CLK1, nCLK1
CLK1, nCLK1
Minimum Typical Maximum Units
2
V_DD + 0.3
V
-0.3
-0.3
0.15
GND + 0.5
0.8
V
0.8
V
±150
µA
1.3
V
V_DD - 0.85 V
V_OH
Output High Voltage
I_OH = -15mA
1.8
V
V
Output Low Voltage
OL
I = 15mA
OL
0.6
V
NOTE 1: Common mode voltage is defined as V_IH.
NOTE 2: For single ended applications, the maximum input voltage for CLK1 and nCLK1 is V + 0.3V.
DDA
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum Typical
f_REF
Input Reference Frequency
Maximum Units
250
MHz
TABLE 6A. AC CHARACTERISTICS, V_DDA = V_DDO = 3.3V±5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
QA ÷2
250
f_MAX
Output Frequency
Qx ÷4
QB, QC, QD ÷8
125
62.5
f_VCO
PLL VCO Lock Range
t(Ø)
Static Phase Offset; ^CLK0
NOTE 1,3
CLK1,
nCLK1
fREF = 50MHz_,
Feedback = VCO/8
250
-135
-420
500
170
-100
tsk(o) Output Skew; NOTE 2, 3
270
tjit(cc)
Cycle-to-Cycle Jitter, RMS;
NOTE 3
All Outputs @ Same Frequency
7.5
t_LOCK
PLL Lock Time; NOTE 3
10
t_R / t_F
Output Rise/Fall Time
20% to 80%
300
800
odc
Output Duty Cycle
46
54
t_PZL
Output Enable Time
6
t_PLZ, t_PHZ Output Disable Time
7
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: Defined as the time difference between the input reference clock and the averaged feedback input signal,
when the PLL is locked and the input reference frequency is stable.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at V_DDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
Units
MHz
MHz
MHz
MHz
ps
ps
ps
ps
mS
ps
%
ns
ns
IDT^™ / ICS^™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
6
ICS87951I-147 REV A JUNE 21, 2006