ICS87951I-147 Datasheet, PDF (10/15 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TOLVCMOS ZERO DELAY BUFFER

ICS87951I-147
LOW SKEW, 1-TO-9, DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CLK INPUT:
For applications not requiring the use of a clock input, it can be
left floating. Though not required, but for additional protection, a
1kΩ resistor can be tied from the CLK input to ground.
OUTPUTS:
LVCMOS OUTPUT:
All unused LVCMOS output can be left floating. There should be
no trace attached.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both V and V must meet the
SWING
OH
V and V input requirements. Figures 3A to 3D show interface
PP
CMR
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 3A, the input termination applies for ICS
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
1.8V
Zo = 50 Ohm
Zo = 50 Ohm
LVHSTL
ICS
HiPerClockS
LVHSTL Driver
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
50
50
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
50
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
Zo = 50 Ohm
LVPECL
Zo = 50 Ohm
3.3V
R3
R4
125
125
3.3V
CLK
nCLK _HiPerClockS
Input
R1
R2
84
84
3.3V
Zo = 50 Ohm
LVDS_Driv er
R1
100
Zo = 50 Ohm
3.3V
CLK
nCLK _{Receiv er}
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
IDT^™ / ICS^™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
10
ICS87951I-147 REV A JUNE 21, 2006