ICS87951I-147 Datasheet, PDF (1/15 Pages) Integrated Device Technology – LOW SKEW, 1-TO-9 DIFFERENTIAL-TOLVCMOS ZERO DELAY BUFFER

LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-
LVCMOS ZERO DELAY BUFFER
GENERAL DESCRIPTION
The ICS87951I-147 is a low voltage, low skew 1-
ICS
to-9 Differential-to-LVCMOS/LVTTL Zero Delay
HiPerClockS™ _{Buffer and a member of the HiPerClockS™family}
of High Performance Clock Solutions from ICS.
The ICS87951I-147 has two selectable clock in-
puts. The single ended clock input accepts LVCMOS or LVTTL
input levels. The CLK1, nCLK1 pair can accept most standard
differential input levels. With output frequencies up to 180MHz,
the ICS87951I-147 is targeted for high performance clock
applications. Along with a fully integrated PLL, the ICS87951I-
147 contains frequency configurable outputs and an external
feedback input for regenerating clocks with “zero delay”.
ICS87951I-147
FEATURES
• Fully integrated PLL
• Nine single ended 3.3V or 2.5V LVCMOS/LVTTL outputs
• Selectable single ended CLK0 or
differential CLK1, nCLK1 inputs
• The single ended CLK0 input can accept the following
input levels: LVCMOS or LVTTL input levels
• CLK1, nCLK1 supports the following input types:
LVDS, LVPECL, LVHSTL, SSTL, HCSL
• Output frequency range: 31.25MHz to 200MHz
• VCO range: 250MHz to 500MHz
• External feedback for ”zero delay” clock regeneration
• Cycle-to-cycle jitter, RMS: 7ps (maximum)
• Output skew: 270ps (maximum)
• Full 3.3V operating supply at -40°C to 85°C ambient
operating temperature
• Full 2.5V operating supply at 0°C to 85°C ambient
operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PIN ASSIGNMENT
VDDA
EXT_FB
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
CLK1
32 31 30 29 28 27 26 25
1
24
2
23
3
22
4 _{ICS87951I-147} 21
5
20
6
19
7
18
8
17
9 10 11 12 13 14 15 16
QC0
VDDO
QC1
GND
QD0
VDDO
QD1
GND
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y package
Top View
IDT^™ / ICS^™ DIFFERENTIAL-TO-LVCMOS ZERO DELAY BUFFER
1
ICS87951I-147 REV A JUNE 21, 2006