ICS873991-147 Datasheet, PDF (7/17 Pages) Integrated Device Technology – LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR

ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
TABLE 5. PLL INPUT REFERENCE CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical
t_R / t_R
Input Rise/Fall Time REF_CLK
Feedback ÷ 6
66.66
Reference Frequency
VCO_SEL = 0
Feedback ÷ 8
Feedback ÷ 16
Feedback ÷ 24
50
25
16.66
Feedback ÷ 32
12.5
f_REF
Feedback ÷ 4
50
Feedback ÷ 6
33.33
Reference Frequency
VCO_SEL = 1
Feedback ÷ 8
25
Feedback ÷ 16
12.5
Feedback ÷ 24
8.33
Feedback ÷ 32
6.25
f_REFDC
Reference Input Duty Cycle
25
NOTE: These parameters are guaranteed by design, but are not tested in production.
Maximum
3
166.67
125
62.5
41.67
31.25
100
66.66
50
25
16.66
12.5
75
Units
ns
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%
TABLE 6. AC CHARACTERISTICS, V_CC = V_CCA = V_CCO = 3.3V ± 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
QA, QB, QC
500
f_MAX
Output Frequency QD
SYNC_SEL = 1
400
QD; NOTE 1
SYNC_SEL = 0
200
t(Ø)
Static Phase Offset;
NOTE 2, 3
PCLK, nPCLK
170
tsk(o) Output Skew; NOTE 4, 5
70
tsk(w) Multiple Frequency Skew; NOTE 5, 6
TBD
tjit(cc) Cycle-to-Cycle Jitter; NOTE 5
35
PLL_SEL = 0
0.4
1.0
f_VCO
PLL VCO Lock Range; NOTE 7
PLL_SEL = 1
200
480
t_LOCK
t
R
/
t_F
odc
PLL Lock Time
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
10
0.5
50
All parameters measured at f_MAX unless noted otherwise.
NOTE 1: SYNC output (QD when SYNC_SEL = 0) operation guaranteed to 800MHz maximum VCO frequency.
NOTE 2: Defined as the time difference between the input reference clock and the average feedback input signal
when the PLL is locked and the input reference frequency is stable.
NOTE 3: Static phase offset is specified for an input frequency of 50MHz with feedback in ÷8.
NOTE 4: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew across banks of outputs switching in the same direction operating at different frequencies
with the same supply voltages and equal load conditions. Measured at V_CCO/2.
NOTE 7: When VCO_SEL = 0, the PLL will be unstable with feedback configurations of ÷2, ÷4 and some ÷6.
When VCO_SEL = 1, the PLL will be unstable with a feedback configuration of ÷2.
Units
MHz
MHz
MHz
ps
ps
ps
ps
GHz
MHz
ms
ns
%
IDT^™ / ICS^™ LVPECL/ECL CLOCK GENERATOR
7
ICS873991AY-147 REV. A AUGUST 10, 2007