ICS873991-147 Datasheet, PDF (12/17 Pages) Integrated Device Technology – LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR

ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
POWER CONSIDERATIONS
PRELIMINARY
This section provides information on power dissipation and junction temperature for the ICS873991-147.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS873991-147 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5% = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
• Power (core) = V * I = 3.465V * 150mA = 519.75mW
MAX
CC_MAX
EE_MAX
• Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 14 * 30mW = 420mW
Total Power (3.465V, with all outputs switching) = 519.75mW + 420mW = 939.75mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockS^TM devices is 125°C.
The equation for Tj is as follows: Tj = θ_JA * Pd_total + T_A
Tj = Junction Temperature
θ_JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
T = Ambient Temperature
A
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θ must be used. Assuming a
JA
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 55.5°C/W per Table 7 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.940W * 55.5°C/W = 122.2°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θ FOR 52-PIN LQFP FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
Multi-Layer PCB, JEDEC Standard Test Boards
63.7°C/W
55.5°C/W
2.5
52.4°C/W
IDT^™ / ICS^™ LVPECL/ECL CLOCK GENERATOR
12
ICS873991AY-147 REV. A AUGUST 10, 2007