ICS873991-147 Datasheet, PDF (4/17 Pages) Integrated Device Technology – LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR

ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
TABLE 2. PIN CHARACTERISTICS
Symbol
C_IN
R_PULLDOWN
R_PULLup
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
4
51
51
Maximum
Units
pF
kΩ
kΩ
TABLE 3A. SELECT PIN FUNCTION TABLE
FSEL3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Inputs
FSEL2 FSEL1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
FSEL0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Outputs
QAx QBx QCx
÷2 ÷2 ÷2
÷2 ÷2 ÷4
÷2 ÷4 ÷4
÷2 ÷2 ÷6
÷2 ÷6 ÷6
÷2 ÷4 ÷6
÷2 ÷4 ÷8
÷2 ÷6 ÷8
÷2 ÷2 ÷8
÷2 ÷8 ÷8
÷4 ÷4 ÷6
÷4 ÷6 ÷6
÷4 ÷6 ÷8
÷6 ÷6 ÷8
÷6 ÷8 ÷8
÷8 ÷8 ÷8
TABLE 3B. FEEDBACK CONTROL FUNCTION TABLE
FSEL_FB2
0
0
0
0
1
1
1
1
Inputs
FSEL_FB1
0
0
1
1
0
0
1
1
FSEL_FB0
0
1
0
1
0
1
0
1
Outputs
QFB
÷2
÷4
÷6
÷8
÷8
÷16
÷24
÷32
TABLE 3C. INPUT CONTROL FUNCTION TABLE
Control Input Pin
PLL_EN
VCO_SEL
REF_SEL
MR
SYNC_SEL
Logic 0
Enables PLL
fVCO
Selects PCLK/nPCLK
---
Selects outputs
Logic 1
Bypasses PLL
fVCO/2
Selects REF_CLK
Resets outputs
Match QC Outputs
IDT^™ / ICS^™ LVPECL/ECL CLOCK GENERATOR
4
ICS873991AY-147 REV. A AUGUST 10, 2007