ICS873991-147 Datasheet, PDF (10/17 Pages) Integrated Device Technology – LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR

ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
LVPECL CLOCK INPUT INTERFACE
The PCLK/nPCLK accepts LVPECL, CML, SSTL and other
differential signals. Both V and V must meet the V and
SWING
OH
PP
V input requirements. Figures 4A to 4E show interface
CMR
examples for the HiPerClockS PCLK/nPCLK input driven by
the most common driver types. The input interfaces suggested
here are examples only. If the driver is from another vendor,
use their termination recommendation. Please consult with the
vendor of the driver component to confirm the driver termination
requirements.
3.3V
CML
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R1
R2
50
50
3.3V
PCLK
nPCLK _HiPerClockS
PCLK/nPCLK
FIGURE 4A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
3.3V
Zo = 50 Ohm
3.3V
R1
PCLK
100
nPCLK
Zo = 50 Ohm
HiPerClockS
CML Built-In Pullup
PCLK/nPCLK
FIGURE 4B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
Zo = 50 Ohm
LVPEC L
Zo = 50 Ohm
3. 3V
R3
R4
125
125
3.3V
PCLK
nPCLK _HiPerClockS
Input
R1
R2
84
84
FIGURE 4C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
3.3V
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
3.3V
R3
R4
84
84
C1
C2
R5
100 - 200
R6
100 - 200
R1
R2
125
125
3.3V
PCLK
nPCLK _HiPerClockS
PCLK/nPCLK
FIGURE 4D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
LVDS
Zo = 50 Ohm
R5
100
Zo = 50 Ohm
3.3V
3.3V
R3
R4
1K
1K
C1
PCLK
C2
nPCLK
HiPerClockS
PC L K / n PC L K
R1
R2
1K
1K
FIGURE 4E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
IDT^™ / ICS^™ LVPECL/ECL CLOCK GENERATOR
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ICS873991AY-147 REV. A AUGUST 10, 2007