ICS873991-147 Datasheet, PDF (11/17 Pages) Integrated Device Technology – LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR

ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
PCLK/nPCLK INPUTS
For applications not requiring the use of a differential input, both
the PCLK and nPCLK pins can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from PCLK to ground.
OUTPUTS:
LVPECL OUTPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
Z_o = 50Ω
FOUT
FIN
Z_o = 50Ω
50Ω
RTT =
1
((V_OH + V_OL) / (V_CC – 2)) – 2
Z_o
50Ω
V_CC - 2V
RTT
FOUT
3.3V
125Ω
125Ω
Z_o = 50Ω
FIN
Z_o = 50Ω
84Ω
84Ω
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT^™ / ICS^™ LVPECL/ECL CLOCK GENERATOR
11
ICS873991AY-147 REV. A AUGUST 10, 2007