ICS873991-147 Datasheet, PDF (3/17 Pages) Integrated Device Technology – LOW VOLTAGE, LVCMOS/LVPECL-TO LVPECL/ECL CLOCK GENERATOR

ICS873991-147
LOW VOLTAGE, LVCMOS/LVPECL-TO-LVPECL/ECL CLOCK GENERATOR
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17, 22, 30, 42
18, 19
20, 21
23, 24
25, 26
27
33
36
39
28, 29
31, 32
34, 35
37, 38
40, 41
43, 44
45, 46
47, 48
49, 50
51
52
Name
V_EE
MR
PLL_EN
REF_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0
REF_CLK
PCLK
nPCLK
V_CC
EXT_FB
nEXT_FB
V_CCA
nQFB
QFB
V_CCO
nQD0, QD0
nQD1, QD1
nQC0, QC0
nQC1, QC1
FSEL3
FSEL2
FSEL1
FSEL0
nQC2, QC2
nQB0, QB0
nQB1, QB1
nQB2, QB2
nQB3, QB3
nQA0, QA0
nQA1, QA1
nQA2, QA2
nQA3, QA3
SYNC_SEL
VCO_SEL
Type
Description
Power
Negative supply pin.
Input
Input
Input
Active High Master Reset. When logic HIGH, the internal dividers are
Pulldown
reset causing the true outputs (Qx) to go low and the inverted outputs
(nQx) to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS/LVTTL interface levels.
Pulldown
PLL enable pin. When logic LOW, PLL is enabled. When logic HIGH,
PLL is in bypass mode. LVCMOS/LVTTL interface levels.
Selects between the different reference inputs as the PLL reference
Pulldown source. When logic LOW, selects PCLK/nPCLK. When logic HIGH,
selects REF_CLK. LVCMOS/LVTTL interface levels.
Input Pulldown Feedback frequency select pins. LVCMOS/LVTTL interface levels.
Input
Input
Input
Power
Input
Input
Power
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Pulldown Non-inverting differential LVPECL clock input.
Pullup/
Pulldown
Inverting differential LVPECL clock input. V_CC/2 default when left floating.
Core supply pin.
Pulldown Non-inverting external feedback input.
Pullup/
Pulldown
Inverting external feedback input. V_CC/2 default when left floating.
Analog supply pin.
Output
Differential feedback output pair. LVPECL Interface levels.
Power
Output
Output
Output
Output
Output supply pins.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Input Pulldown Frequency select pins. LVCMOS/LVTTL interface levels.
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Input
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
SYNC output select pin. When LOW, the SYNC otuput follows the
Pulldown timing diagram (page 5). When HIGH, QD output follows QC output
LVCMOS/LVTTL interface levels..
Pulldown Selects VCO range. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
IDT^™ / ICS^™ LVPECL/ECL CLOCK GENERATOR
3
ICS873991AY-147 REV. A AUGUST 10, 2007