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ICS843002I-41 Datasheet, PDF (7/23 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR
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ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
Table 4D. LVPECL DC Characteristics, VCC = VCCO_LVPECL = 3.3V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum
Units
VOH
VOL
VSWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO – 1.4
VCCO – 2.0
0.6
VCCO – 0.9
V
VCCO – 1.7
V
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. See Parameter Measurement Information section, Output Load Test Circuit
diagram.
Table 4E. LVPECL DC Characteristics, VCC = 3.3V±5%, VCCO_LVPECL = 2.5V±5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
VOL
VSWING
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO – 1.4
VCCO – 2.0
0.4
VCCO – 0.9
V
VCCO – 1.5
V
1.0
V
NOTE 1: Outputs terminated with 50Ω to VCCO_LVPECL – 2V. See Parameter Measurement Information section, Output Load
Test Circuit diagram.
AC Electrical Characteristics
Table 5. AC Characteristics, VCC = 3.3V±5%, VCCO_LVCMOS = VCCO_LVPECL = 3.3V±5% or 2.5V±5%, VEE = 0V,
TA = -40°C to 85°C
Parameter Symbol
Test Conditions
Minimum Typical Maximum
fOUT
tsk(o)
Output Frequency
Output Skew; NOTE 1, 2
19.44
700
50
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
155.52MHz,
Integration Range: 12kHz – 20MHz
0.81
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20% to 80%
100
800
45
55
Units
MHz
ps
ps
ps
%
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage, same frequency, and with equal load conditions.
Measured at the output differential cross points.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise plots.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
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ICS843002AKI-41 REV. A OCTOBER 25, 2007
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