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ICS843002I-41 Datasheet, PDF (14/23 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR | |||
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ICS843002I-41
700MHZ, FEMTOCLOCKS⢠VCXO BASED SONET/SDH JITTER ATTENUATOR
Termination for 3.3V LVPECL Outputs
The clock layout topology shown below is a typical termination for
LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50â¦
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal
distortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts may
exist and it would be recommended that the board designers
simulate to guarantee compatibility across all printed circuit and
clock component process variations.
Zo = 50â¦
FOUT
FIN
Zo = 50â¦
50â¦
RTT =
1
((VOH + VOL) / (VCC â 2)) â 2
Zo
50â¦
VCC - 2V
RTT
Figure 5A. 3.3V LVPECL Output Termination
FOUT
3.3V
125â¦
125â¦
Zo = 50â¦
FIN
Zo = 50â¦
84â¦
84â¦
Figure 5B. 3.3V LVPECL Output Termination
IDT⢠/ ICS⢠VCXO BASED SONET/SDH JITTER ATTENUATOR
14
ICS843002AKI-41 REV. A OCTOBER 25, 2007
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