ICS843002I-41 Datasheet, PDF (10/23 Pages) Integrated Circuit Systems – 700MHz, FEMTOCLOCKS-TM VCXO BASED SONET/SDH JITTER ATTENUATOR

ICS843002I-41
700MHZ, FEMTOCLOCKS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
nQA, nQB
QA, QB
t _PW
t
PERIOD
odc = ^{t PW} x 100%
t _PERIOD
Output Duty Cycle/Pulse Width/Period
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
CLK/nCLK Inputs
For applications not requiring the use of the differential input, both
CLKx and nCLKx can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from CLKx to
ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
Outputs:
LVPECL Outputs
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
LVCMOS Outputs
All unused LVCMOS output can be left floating. There should be no
trace attached.
IDT™ / ICS™ VCXO BASED SONET/SDH JITTER ATTENUATOR
10
ICS843002AKI-41 REV. A OCTOBER 25, 2007