9ZXL1231_16 Datasheet, PDF (7/18 Pages) Integrated Device Technology – 12-output DB1200ZL

9ZXL1231 DATASHEET
Electrical Characteristics–Input/Supply/Common Output Parameters
T_AMB = T_COM or T_IND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
Output Supply Voltage
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
Input High Voltage
Input Mid Voltage
Input Low Voltage
VDDx
VDDIO
T_AMB
V_IH
V_IL
V_IHTRI
V_IMTRI
V_ILTRI
I_IN
Supply voltage, except VDDIO
Supply voltage for DIF outputs, if present
3.135
3.3
3.465
V
0.95
1.05
3.465
V
Commmercial range (T_COM)
Industrial range (T_IND)
Single-ended inputs, except SMBus, tri-level
inputs
Single-ended inputs, except SMBus, tri-level
inputs
0
-40
2
GND - 0.3
70
°C
85
°C
V_DD + 0.3 V
0.8
V
Tri-Level Inputs
Tri-Level Inputs
2.2
V_DD + 0.3 V
1.2
VDD/2
1.8
V
Tri-Level Inputs
GND - 0.3
0.8
V
Single-ended inputs, V_IN = GND, V_IN = VDD
-5
5
uA
Input Current
Single-ended inputs
I_INP
V_IN = 0 V; Inputs with internal pull-up resistors
-200
V_IN = VDD; Inputs with internal pull-down resistors
200
uA
Input Frequency
Pin Inductance
Capacitance
F_ibyp
F_ipll
F_ipll
L_pin
C_IN
C_{INDIF_IN}
V_DD = 3.3 V, Bypass mode
V_DD = 3.3 V, 100MHz PLL mode
V_DD = 3.3 V, 133.33MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
C_OUT
Output pin capacitance
Clk Stabilization
Input SS Modulation
Frequency PCIe
OE# Latency
T_STAB
f_MODINPCIe
t_LATOE#
From V_DD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency for PCIe Applications
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
t_DRVPD
DIF output enable after
PD# de-assertion
Tfall
t_F
Fall time of control inputs
Trise
t_R
Rise time of control inputs
1_{Guaranteed by design and characterization, not 100% tested in production.}
2_{Control input must be monotonic from 20% to 80% of input swing.}
3_{Time from deassertion until outputs are >200 mV}
4_{DIF_IN input}
33
150
90
100.00 110
120 133.33 147
7
1.5
5
1.5
2.7
6
0.18
1.8
MHz
MHz
MHz
nH
1
pF
1
pF
1,4
pF
1
ms
1,2
30
33
kHz
4
10 clocks 1,2,3
300
us
1,3
5
ns
2
5
ns
2
REVISION J 05/25/16
7
12-OUTPUT DB1200ZL