9ZXL1231_16 Datasheet, PDF (4/18 Pages) Integrated Device Technology – 12-output DB1200ZL

9ZXL1231 DATASHEET
Pin Descriptions
PIN #
PIN NAME
1 VDDA
2 GNDA
3 NC
4 100M_133M#
5 HIBW_BYPM_LOBW#
6 CKPWRGD_PD#
7 GND
8 VDDR
9 DIF_IN
10 DIF_IN#
11 SMB_A0_tri
12 SMBDAT
13 SMBCLK
14 SMB_A1_tri
15 DFB_OUT_NC#
16 DFB_OUT_NC
17 DIF_0
18 DIF_0#
19 vOE0#
20 vOE1#
21 DIF_1
22 DIF_1#
23 GND
24 VDD
25 VDDIO
26 DIF_2
27 DIF_2#
28 vOE2#
29 vOE3#
30 DIF_3
31 DIF_3#
32 VDDIO
33 GND
34 DIF_4
35 DIF_4#
36 vOE4#
37 vOE5#
TYPE
PWR
GND
N/A
IN
IN
IN
GND
PWR
IN
IN
IN
I/O
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
GND
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
GND
OUT
OUT
IN
IN
DESCRIPTION
Power for the PLL core.
Ground pin for the PLL core.
No Connection.
3.3V Input to select operating frequency.
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
See PLL Operating Mode Table for Details.
3.3V Input notifies device to sample latched inputs and start up on first high assertion, or exit Power Down
Mode on subsequent assertions. Low enters Power Down Mode.
Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
filtered appropriately.
HCSL True input
HCSL Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9
SMBus Addresses.
Data pin of SMBUS circuitry, 5V tolerant
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9
SMBus Addresses.
Complementary half of differential feedback output, provides feedback signal to the PLL for
synchronization with input clock to eliminate phase error. This pin should NOT be connected on the circuit
board, the feedback is internal to the package.
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the
input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback
is internal to the package.
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL true clock output
HCSL Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Power supply for differential outputs
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
HCSL true clock output
HCSL Complementary clock output
Power supply for differential outputs
Ground pin.
HCSL true clock output
HCSL Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
12-OUTPUT DB1200ZL
4
REVISION J 05/25/16