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9ZXL1231_16 Datasheet, PDF (1/18 Pages) Integrated Device Technology – 12-output DB1200ZL | |||
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12-output DB1200ZL
9ZXL1231
DATASHEET
General Description
The 9ZXL1231 meets the demanding requirements of the
Intel DB1200ZL specification, including the critical low-drift
requirements of Intel CPUs.
Recommended Application
Buffer for Romley, Grantley and Purley Servers, solid state
storage and PCIe
Output Features
⢠12 - Low-Power (LP) HCSL output pairs
Key Specifications
⢠Cycle-to-cycle jitter <50ps
⢠Output-to-output skew <50 ps
⢠Input-to-output delay variation <50ps
⢠PCIe Gen3 phase jitter <1.0ps RMS
⢠Phase jitter: QPI/UPI >=9.6GB/s <0.2ps rms
Block Diagram
OE(11:0)#
Features/Benefits
⢠Low-power push-pull HCSL outputs; eliminate 24 resistors,
save 41mm2 of area
⢠Pin compatible to 9ZX21201; easy path to >50% power
savings
⢠Space-saving 64 VFQFPN package
⢠Fixed feedback path for 0ps input-to-output delay
⢠9 Selectable SMBus Addresses; multiple devices can
share the same SMBus Segment
⢠12 OE# pins; hardware control of each output
⢠PLL or bypass mode; PLL can dejitter incoming clock
⢠Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
⢠Spread Spectrum Compatible; tracks spreading input clock
for low EMI
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT_NC
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
9ZXL1231 REVISION J 05/25/16
1
©2016 Integrated Device Technology, Inc.
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