9ZXL1231_16 Datasheet, PDF (10/18 Pages) Integrated Device Technology – 12-output DB1200ZL

9ZXL1231 DATASHEET
Electrical Characteristics–Phase Jitter Parameters
T_AMB = T_COM or T_IND, unless noted., Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX IND.LIMIT UNITS Notes
Phase Jitter, PLL Mode
t_jphPCIeG1
t_jphPCIeG2
t_jphPCIeG3
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
34 45.1
86
ps (p-p)
1.2 1.43
3
ps
(rms)
2.2 2.63
3.1
ps
(rms)
0.5 0.59
1
ps
(rms)
0.24 0.32 0.5
ps
(rms)
t_{jphQPI_SMI}
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
0.14 0.23 0.3
0.12 0.18 0.2
ps
(rms)
ps
(rms)
Additive Phase Jitter,
Bypass mode
t_jphPCIeG1
t_jphPCIeG2
t_jphPCIeG3
t_{jphQPI_SMI}
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4 or 2-5 MHz, CDR = 10MHz)
QPI & SMI
(100MHz or 133MHz, 4.8Gb/s, 6.4Gb/s 12UI)
QPI & SMI
(100MHz, 8.0Gb/s, 12UI)
QPI & SMI
(100MHz, 9.6Gb/s, 12UI)
3.7 5.1
n/a
ps (p-p)
0.1 0.2
n/a
ps
(rms)
0.4 0.5
n/a
ps
(rms)
0.0 0.1
n/a
ps
(rms)
0.14 0.2
n/a
ps
(rms)
0.00 0.01 n/a
ps
(rms)
0.00 0.01 n/a
ps
(rms)
1 _{Applies to all outputs.}
2 _{See http://www.pcisig.com for complete specs}
3 _{Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.}
4 _{Calculated from Intel-supplied Clock Jitter Tool v 1.6.3}
5 _{For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jittter)^2 - (input jitter)^2]}
1,2,3
1,2
1,2
1,2,4
1,4
1,4
1,4
1,2,3
1,2,5
1,2,5
1,2,4,5
1,4,5
1,4,5
1,4,5
12-OUTPUT DB1200ZL
10
REVISION J 05/25/16