7005S55PFG Datasheet, PDF (7/21 Pages) Integrated Device Technology – HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
5V
5V
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns Max.
1.5V
1.5V
Figures 1 and 2
DATAOUT
BUSY
INT
775Ω
1250Ω
30pF
DATAOUT
775Ω
1250Ω
5pF*
2738 tbl 12
Figure 1. AC Output Test Load
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range⁽⁴⁾
2738 drw 06
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig
7005X15
Com'l Only
7005X17
Com'l Only
7005X20
Com'l, Ind
& Military
7005X25
Com'l &
Military
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
tAA
Address Access Time
tACE
Chip Enable Access Time⁽³⁾
tAOE
Output Enable Access Time
tOH
Output Hold from Address Change
tLZ
Output Low-Z Time^(1,2)
tHZ
Output High-Z Time^(1,2)
tPU
Chip Enable to Power Up Time^(2,5)
tPD
Chip Disable to Power Down Time^(2,5)
tSOP
Semaphore Flag Update Pulse (OE or SEM)
tSAA
Semaphore Address Access Time
Symbol
Parameter
15
____
17
____
20
____
25
____
ns
____
15
____
17
____
20
____
25
ns
____
15
____
17
____
20
____
25
ns
____
10
____
10
____
12
____
13
ns
3
____
3
____
3
____
3
____
ns
3
____
3
____
3
____
3
____
ns
____
10
____
10
____
12
____
15
ns
0
____
0
____
0
____
0
____
ns
____
15
____
17
____
20
____
25
ns
10
____
10
____
10
____
10
____
ns
____
15
____
17
____
20
____
25
ns
7005X35
Com'l, Ind
& Military
7005X55
Com'l, Ind
& Military
2738 tbl 13a
IDT7005X70
Military
Only
Min. Max. Min. Max. Min. Max. Unit
READ CYCLE
tRC
Read Cycle Time
35
____
55
____
70
____
ns
tAA
Address Access Time
____
35
____
55
____
70
ns
tACE
Chip Enable Access Time⁽³⁾
____
35
____
55
____
70
ns
tAOE
Output Enable Access Time
____
20
____
30
____
35
ns
tOH
Output Hold from Address Change
3
____
3
____
3
____
ns
tLZ
Output Low-Z Time^(1,2)
3
____
3
____
3
____
ns
tHZ
Output High-Z Time^(1,2)
____
15
____
25
____
30
ns
tPU
Chip Enab le to Power Up Time^(2,5)
0
____
0
____
0
____
ns
tPD
Chip Disable to Power Down Time^(2,5)
____
35
____
50
____
50
ns
tSOP
Semaphore Flag Update Pulse (OE or SEM)
15
____
15
____
15
____
ns
tSAA
Semaphore Address Access Time
____
35
____
55
____
70
ns
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with load (Figures 1 and 2).
2. This parameter is guaranteed but not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
2738 tbl 13b
6.742