7005S55PFG Datasheet, PDF (3/21 Pages) Integrated Device Technology – HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM

IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations^(1,2,3) (con't.)
11/19/01
11
51 50 48 46 44 42 40 38 36
A5L A4L A2L A0L BUSYL _M/S INTR A1R A3R
53 52 49 47 45 43 41 39 37 35 34
10 _{A7L A6L A3L A1L INTL GND BUSYR A0R A2R A4R A5R}
55 54
09 _{A9L A8L}
32 33
A7R A6R
57 56
08 _{A11L A10L}
30 31
A9R A8R
59 58
07 _{VCC A12L}
61 60
06 _{N/C N/C}
63 62
05 _{SEML CEL}
IDT7005G
G68-1(4)
68-Pin PGA
Top View(5)
28 29
A11R A10R
26 27
GND A12R
24 25
N/C N/C
65 64
04 _{OEL R/WL}
22 23
SEMR CER
67 66
03 _{I/O0L N/C}
20 21
OER R/WR
68 1
3
5
7
9
11 13 15 18 19
02 _{I/O1L I/O2L I/O4L GND I/O7L GND I/O1R VCC I/O4R I/O7R N/C}
,
2
4
6
8
10 12 14 16 17
01
I/O3L I/O5L I/O6L VCC I/O0R I/O2R I/O3R I/O5R I/O6R
ABCDE
INDEX
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.18in x 1.18in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate oriention of the actual part-marking
FG
H
J
K
L
2738 drw 04
Pin Names
Left Port
Right Port
CEL
CER
R/WL
R/WR
OEL
OER
A0L - A12L
A0R - A12R
I/O0L - I/O7L
I/O0R - I/O7R
SEML
SEMR
INTL
INTR
BUSYL
BUSYR
M/S
VCC
GND
Names
Chip Enable
Read/Write Enable
Output Enable
Address
Data Input/Output
Semaphore Enable
Interrupt Flag
Busy Flag
Master or Slave Select
Power
Ground
2738 tbl 01
6.342