ICS9LPRS525_10 Datasheet, PDF (6/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
NOTES on Input/Supply/Common Output DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{Signal is required to be monotonic in this region.}
2 _{input leakage current does not include inputs with pull-up or pull-down resistors}
3 _{3.3V referenced inputs are: PCI_STOP#, CPU_STOP#, TME, SRC5_EN, ITP_EN, SCLKL, SDATA, TESTMODE, TESTSEL, CKPWRGD and CR# inputs if selected.}
4 _{Intentionally blank}
5 _{Maximum VIH is not to exceed VDD}
6 _{Human Body Model}
7 _{Operation under these conditions is neither implied, nor guaranteed.}
8 _{Frequency Select pins which have tri-level input}
9 _{PCI3/CFG0 is optional}
10 _{If present. Not all parts have this feature.}
AC Electrical Characteristics - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX UNITS NOTES
Rising Edge Slew Rate
tSLR
Averaging on
2.5
4
V/ns 2, 3
Falling Edge Slew Rate
tFLR
Averaging on
2.5
4
V/ns 2, 3
Slew Rate Variation
tSLVAR
Averaging on
20
% 1, 10
Differential Voltage Swing
VSWING
Averaging off
300
mV
2
Crossing Point Voltage
VXABS
Averaging off
300
550
mV 1,4,5
Crossing Point Variation
VXABSVAR
Averaging off
140
mV 1,4,9
Maximum Output Voltage
VHIGH
Averaging off
1150
mV 1,7
Minimum Output Voltage
VLOW
Averaging off
-300
mV 1,8
Duty Cycle
DCYC
Averaging on
45
55
%
2
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
CPU[2_ITP:0] Skew
CPUSKEW20
Differential Measurement
150
ps
1
SRC[10:0] Skew
SRCSKEW
Differential Measurement
3000
ps
1,6
NOTES on DIF Output AC Specs: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
1_{Measurement taken for single ended waveform on a component test board (not in system)}
2 _{Measurement taken from differential waveform on a component test board. (not in system)}
3 _{Slew rate emastured through V_swing voltage range centered about differential zero}
4 _{Vcross is defined at the voltage where Clock = Clock#, measured on a component test board (not in system)}
5 _{Only applies to the differential rising edge (Clock rising, Clock# falling)}
6 _{Total distributed intentional SRC to SRC skew. Maximum allowable interpair skew is 150 ps.}
7 _{The max voltage including overshoot.}
8 _{The min voltage including undershoot.}
9 _{The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross absolute) allowed. The intent is to limit Vcross}
induced modulation by setting C_cross_delta to be smaller than V_Cross absolute
10 _{Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on the average cross point where Clock rising}
meets Clock# falling. The median cross point is used to calculate the voltage
Clock Jitter Specs - Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
CPU Jitter - Cycle to Cycle
CPUJC2C
Differential Measurement
SRC Jitter - Cycle to Cycle
SRCJC2C
Differential Measurement
DOT Jitter - Cycle to Cycle
DOTJC2C
Differential Measurement
NOTES on DIF Output Jitter: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).
MAX
85
125
250
UNITS NOTES
ps
1
ps
1
ps
1
1_{Jitter specs are specified as measured on a clock characterization board. System designers need to take special care not to use these numbers, as the in-system performance}
will be somewhat degraded. The receiver EMTS (chispet or CPU) will have the receiver
IDT^TM PC MAIN CLOCK
6
1484B—01/21/10