ICS9LPRS525_10 Datasheet, PDF (3/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Pin Description (continued)
PIN #
PIN NAME
25 SRCC3_LRS/CR#_D
26 VDDSRCIO
TYPE
I/O
PWR
DESCRIPTION
Complementary clock of low power differential SRC clock pair with integrated 33 ohm Rs/ Clock Request control D for either SRC1 or SRC4 pair.
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before
configuring this pin as a Clock Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC output is
disabled, the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CRD#_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CRD# enabled. Byte 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CRD# controls SRC1 pair (default),
1= CRD# controls SRC4 pair
Power supply for SRC outputs. 1.05V to 3.3V.
27 SRCT4_LRS
OUT
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
28 SRCC4_LRS
29 CPU_STOP#/SRCC5_LRS
30 PCI_STOP#/SRCT5_LRS
31 VDDSRC
OUT
I/O
I/O
PWR
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
Stops all CPUCLK, except those set to be free running clocks /
Complement clock of low power differential SRC pair with 33 ohm integrated Rs.
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by this input. / True clock of low power differential SRC pair
with integrated 33 ohm Rs.
Supply for SRC PLL, 3.3V nominal
32 SRCC6_LRS
OUT
Complement clock of low power differential SRC clock pair with 33 ohm integrated Rs.
33 SRCT6_LRS
OUT
True clock of low power differential SRC clock pair with integrated 33 ohm Rs.
34 GNDSRC
35 SRCC7_LRS/CR#_E
36 SRCT7_LRS/CR#_F
37 VDDSRCIO
38 CPUC2_ITP_LRS/SRCC8_LRS
39 CPUT2_ITP_LRS/SRCT8_LRS
PWR
I/O
I/O
PWR
OUT
OUT
Ground pin for the SRC outputs
Complement clock of differential push-pull SRC clock pair with 33 ohm integrated Rs. / Clock Request control E for SRC6 pair. The power-up default
is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the
SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CRE# enabled.
True clock of differential push-pull SRC clock pair/ Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock
Request Pin, the SR
Power supply for SRC outputs. 1.05V to 3.3V.
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. 33 ohm Rs is integrated. The function of this pin is determined by the
latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
40 NC
41 VDDCPUIO
N/A
PWR
No Connect
Power supply for CPU outputs, 1.05V to 3.3V.
42 CPUC1_F_LRS
OUT
Complementary clock of low power differential push-pull CPU output with integrated 33 ohm Rs. This CPU clock is free running during iAMT.
43 CPUT1_F_LRS
44 GNDCPU
45 CPUC0_LRS
46 CPUT0_LRS
47 VDDCPU
48 CK_PWRGD/PD#
49 FSLB/TEST_MODE
50 GNDREF
51 X2
52 X1
53 VDDREF
54 REF0/FSLC/TEST_SEL
55 SDATA
56 SCLK
OUT
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
True clock of differential push-pull CPU clock pair with integrated 33 ohm Rs. This clock is free running during iAMT.
Ground pin for the CPU outputs
Complement clock of low power differential CPU clock pair with integrated 33 ohm Rs.
True clock of low power differential CPU clock pair with integrated 33 ohm Rs.
Supply for CPU PLL, 3.3V nominal
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. TEST_MODE is a real time
input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test Clarification Table.
Ground pin for the REF outputs.
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.
/TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
IDT^TM PC MAIN CLOCK
3
1484B—01/21/10