ICS9LPRS525_10 Datasheet, PDF (16/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Byte 8 Device ID and Output Enable Register
Bit Pin
Name
Description
7
Device_ID3
Table of Device identifier codes, used for
6
Device_ID2
differentiating between CK505 package options,
5
Device_ID1
etc.
4
Device_ID0
3
Reserved
Reserved
2
Reserved
Reserved
1
SE1_OE
0
SE2_OE
Output enable for SE1
Output enable for SE2
Type
R
R
R
R
RW
RW
RW
RW
0
1
56-pin device
-
-
Disabled
Disabled
-
-
Enabled
Enabled
Default
0
0
0
0
0
0
0
0
Byte 9 Output Control Register
Bit Pin
Name
Description
Allows control of PCIF5 with assertion of
7
PCIF5 STOP EN
PCI_STOP#
6
TME_Readback
Truested Mode Enable (TME) strap status
5
REF Strength
Sets the REF output drive strength
4
Test Mode Select
Allows test select, ignores REF/FSC/TestSel
3
Test Mode Entry
Allows entry into test mode, ignores
FSB/TestMode
2
IO_VOUT2
IO Output Voltage Select (Most Significant Bit)
1
IO_VOUT1
IO Output Voltage Select
0
IO_VOUT0
IO Output Voltage Select (Least Significant Bit)
Type
RW
R
RW
RW
0
Free running
normal operation
1X (2Loads)
Outputs HI-Z
1
Default
Stops with
PCI_STOP#
0
assertion
no overclocking Latch
2X (3 Loads)
1
Outputs = REF/N 0
RW Normal operation Test mode
0
RW
See Table 3: V_IO Selection
1
RW
(Default is 0.8V)
0
RW
1
Byte 10 Stop Enable Register
Bit Pin
Name
7
SRC5_EN Readback
6
Reserved
5
Reserved
4
Reserved
3
Reserved
2
Reserved
1
CPU 1 Stop Enable
0
CPU 0 Stop Enable
Description
Readback of SRC5 enable latch
Reserved
Enables control of CPU1 with CPU_STOP#
Enables control of CPU 0 with CPU_STOP#
Type
R
RW
RW
RW
RW
RW
RW
RW
0
CPU/PCI Stop
Enabled
-
-
-
-
-
Free Running
Free Running
1
Default
SRC5 Enabled Latch
-
0
-
0
-
0
-
0
-
0
Stoppable
1
Stoppable
1
Byte 11 iAMT Enable Register
Bit Pin
Name
Description
7
PCI3_CFG1
See PCI3 Configuration Table 28
6
PCI3_CFG0
5
Reserved
Reserved
4
Reserved
Reserved
3
CPU2_AMT_EN
Determines if CPU2 runs in M1 mode.
Only valid if ITP_EN=1. See Note.
2
CPU1_AMT_EN
Determines if CPU1 runs in M1 mode. See Note.
Type
R
R
RW
RW
RW
RW
1
PCI-E_GEN2
Determines if PCI-E Gen2 compliant
R
0
CPU 2 Stop Enable
Enables control of CPU 0 with CPU_STOP# RW
NOTE: A value of '00' for Bit(3:2) in Byte 11 is reserved and not a valid configuration.
0
1
See PCI3 Configuration Table
-
-
-
-
Does not Run
Runs
Does not Run
non-Gen2
Free Running
Runs
PCI-E Gen2
Compliant
Stoppable
Default
Latch
Latch
0
1
0
1
1
1
IDT^TM PC MAIN CLOCK
16
1484B—01/21/10