ICS9LPRS525_10 Datasheet, PDF (20/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
N
INDEX
AREA
12
D
A2
e
b
c
L
E1 E
a
A
A1
-C-
SEATING
PLANE
aaa C
56-Lead 6.10 mm. Body, 0.50 mm. Pitch TSSOP
(240 mil)
(20 mil)
In Millimeters
In Inches
SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
--
1.20
--
.047
A1
0.05
0.15
.002
.006
A2
0.80
1.05
.032
.041
b
0.17
0.27
.007
.011
c
0.09
0.20
.0035
.008
D
SEE VARIATIONS
SEE VARIATIONS
E
8.10 BASIC
0.319 BASIC
E1
6.00
6.20
.236
.244
e
0.50 BASIC
0.020 BASIC
L
0.45
0.75
.018
.030
N
SEE VARIATIONS
SEE VARIATIONS
α
0°
8°
0°
8°
aaa
--
0.10
--
.004
VARIATIONS
N
D mm.
MIN
MAX
56
13.90
14.10
Reference Doc.: JEDEC Publicat ion 95, M O-153
10 -0 0 3 9
D (inch)
MIN
MAX
.547
.555
Ordering Information
9LPRS525AGLFT
Example:
XXXX A G LF T
Designation for tape and reel packaging
Lead Free, RoHS Compliant
Package Type
G = TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type
IDT^TM PC MAIN CLOCK
20
1484B—01/21/10