ICS9LPRS525_10 Datasheet, PDF (5/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Absolute Maximum Ratings - DC Parameters
PARAMETER
SYMBOL
CONDITIONS
Maximum Supply Voltage
VDDxxx
Supply Voltage
Maximum Supply Voltage
VDDxxx_IO
Low-Voltage Differential I/O Supply
Maximum Input Voltage
V_IH
3.3V Inputs
Minimum Input Voltage
V_IL
Any Input
Storage Temperature
Ts
-
Input ESD protection
ESD prot
1_{Guaranteed by design and characterization, not 100% tested in production.}
Human Body Model
2 _{Operation under these conditions is neither implied, nor guaranteed.}
3 _{Maximum input voltage is not to exceed VDD}
MIN
GND - 0.5
-65
2000
MAX
4.6
3.8
4.6
150
UNITS
V
V
V
V
°_C
V
Notes
7
7
4,5,7
4,7
4,7
6,7
Electrical C haracteristics - Input/S upply/C ommon Output D C Parameters
PARAMETER
A m bient Operating Tem p
Supply Voltage
Supply Voltage
Input High Voltage
Input Low Voltage
Low Threshold Input- High Voltage
Low Thres hold Input- FS C = '1'
V olt age
Low Threshold Input- FS A ,FSB = '1'
V olt age
Low Threshold Input-Low Voltage
PCI3/CFG0 Input
PCI3/CFG0 Input
PCI3/CFG0 Input
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
iAM T M ode Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
Clk Stabilization
T driv e_CR_of f
T driv e_CR_on
Tdriv e_CPU
Tf all_S E
T ris e_S E
SMBus Voltage
Low-level Output Voltage
Current sinking at V _OLSMB = 0.4 V
SCLK/SDATA
Clock/Data Rise Time
SCLK/SDATA
Clock/Data Fall Time
M ax im um S M B us Operating
F requenc y
Spread Spectrum M odulation
F requenc y
SYMBOL
T am bient
VDDxxx
VDDxxx_IO
V _IHSE
V _ILSE
V _{IH_FS_TEST}
V _{IH_FS_FSC}
CONDITIONS
-
Supply Voltage
Low-Voltage Differential I/O Supply
Single-ended 3.3V inputs
Single-ended 3.3V inputs
3.3 V +/-5%
3.3 V +/-5%
MIN
0
3.135
0.9975
2
V_SS - 0.3
2
MAX UNITS
70
°C
3.465
V
3.465
V
V _DD + 0.3 V
0.8
V
VDD + 0.3 V
Notes
10
3
3
8
0.7
1.5
V
8
V _{IH_FS_FSAB}
V _{IL_FS}
V _{IL_CFGHI}
V _{IL_CFGMID}
V _{IL_CFGLO}
I_IN
I _{I NRE S}
V _OHSE
V_OLSE
I _{DDO P 3 . 3}
I _{DDO P I O}
I _{DDiA MT3 . 3}
I _{DDiA MTI O}
I _{DDP D3 . 3}
I _{DDP DI O}
F_i
L_pin
C_IN
C _{O UT}
C _{I NX}
T _{S TA B}
T _{DRCRO FF}
T _{DRCRO N}
T _{DRS RC}
T _{FA L L}
T _{RI S E}
V _DD
V _OLSMB
I _{P UL L UP}
T _{RI 2C}
T _{FI 2 C}
F _{S MB US}
3.3 V +/-5%
3.3 V +/-5%
Optional input, 2.75V typ.
Optional input, 1.65V typ.
Optional input, 0.55V typ.
V_IN = V _{DD ,} V _IN = GND
Inputs with pull up or pull down resistors
V_IN = V _{DD ,} V _IN = GND
Single-ended outputs, I_OH = -1m A
Single-ended outputs, I_OL = 1 m A
Full Active, C_L = Full load; Idd 3.3V
Full Active, C_L = Full load; IDD IO
M1 mode, 3.3V Rail
M1 Mode, IO Rail
Power down mode, 3.3V Rail
Power down mode, IO Rail
V_DD = 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
From VDD Power-Up or de-assertion of PD to 1st
c loc k
Output stop after CR deasserted
Output run after CR asserted
CPU output enable after
P CI_S TOP # de-as sertion
Fall/rise time of all 3.3V control inputs from 20-80%
@ I_PULLUP
SMB Data Pin
(Max VIL - 0.15) to
(M in V IH + 0.15)
(Min VIH + 0.15) to
(Max VIL - 0.15)
0.7
V_SS - 0.3
2.4
1.3
V_SS - 0.3
-5
-200
2.4
1.5
2.7
4
VDD+0.3
0.35
VDD+0.3
2
0.9
5
200
0.4
115
55
36
10
5
0.1
15
7
5
6
6
1.8
400
0
10
10
10
5.5
0.4
1000
300
100
V
V
V
V
V
uA
uA
V
V
mA
mA
mA
mA
mA
mA
MHz
nH
pF
pF
pF
ms
ns
us
ns
ns
ns
V
V
mA
ns
ns
kHz
9, 10
9, 10
9, 10
2
1
1
10
10
f _{S S MO D}
Triangular Modulation
30
33
kHz
IDT^TM PC MAIN CLOCK
1484B—01/21/10
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