ICS9LPRS525_10 Datasheet, PDF (14/21 Pages) Integrated Device Technology – 56-pin CK505 for Intel Systems

ICS9LPRS525
PC MAIN CLOCK
Byte 0 FS Readback and PLL Selection Register
Bit Pin
Name
Description
Type
0
1
Default
7-
6-
5-
4-
3
FSLC
FSLB
FSLA
iAMT_EN
Reserved
CPU Freq. Sel. Bit (Most Significant)
CPU Freq. Sel. Bit
CPU Freq. Sel. Bit (Least Significant)
Set via SMBus or dynamically by CK505 if detects
dynamic M1
Reserved
R _{See Table 1 : CPU Frequency Select}
R
Table
R
RW Legacy Mode iAMT Enabled
RW
Latch
Latch
Latch
0
0
2-
SRC_Main_SEL
Select source for SRC Main
RW SRC Main = PLL1 SRC Main = PLL3 Latch
1-
0-
SATA_SEL
PD_Restore
Select source for SATA clock
RW
SATA =
SRC_Main
SATA = PLL2
0
1 = on Power Down de-assert return to last known
state
0 = clear all SMBus configurations as if cold power-
on and go to latches open state
RW
Configuration Not
Saved
Configuration
Saved
1
This bit is ignored and treated at '1' if device is in
iAMT mode.
Byte 1 DOT96 Select and PLL3 Quick Config Register
Bit Pin
Name
Description
7 13/14
SRC0_SEL
Select SRC0 or DOT96
6-
PLL1_SSC_SEL
Select 0.5% down or center SSC
5
PLL3_SSC_SEL
Select 0.5% down or center SSC
4
PLL3_CF3
PLL3 Quick Config Bit 3
3
PLL3_CF2
PLL3 Quick Config Bit 2
2
PLL3_CF1
PLL3 Quick Config Bit 1
1
PLL3_CF0
PLL3 Quick Config Bit 0
0
PCI_SEL
PCI_SEL
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
SRC0
Down spread
Down spread
1
DOT96
Center spread
Center spread
See Table 2: PLL3 Quick
Configuration
Only applies if Byte 0, bit 2 = 0.
PCI from PLL1
PCI from
SRC_MAIN
Default
0
Latch
0
0
0
0
1
1
Byte 2 Output Enable Register
Bit Pin
Name
Description
7
REF_OE
Output enable for REF, if disabled output is tri-
stated
6
USB_OE
Output enable for USB
5
PCIF5_OE
Output enable for PCI5
4
PCI4_OE
Output enable for PCI4
3
PCI3_OE
Output enable for PCI3
2
PCI2_OE
Output enable for PCI2
1
PCI1_OE
Output enable for PCI1
0
PCI0_OE
Output enable for PCI0
Type
0
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
RW Output Disabled
1
Default
Output Enabled 1
Output Enabled 1
Output Enabled 1
Output Enabled 1
Output Enabled 1
Output Enabled 1
Output Enabled 1
Output Enabled 1
Byte 3 Output Enable Register
Bit Pin
Name
7
Reserved
6
Reserved
5
Reserved
4
SRC8/ITP_OE
3
SRC7_OE
2
SRC6_OE
1
SRC5_OE
0
SRC4_OE
Description
Reserved
Reserved
Reserved
Output enable for SRC8 or ITP
Output enable for SRC7
Output enable for SRC6
Output enable for SRC5
Output enable for SRC4
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
Output Disabled
Output Disabled
Output Disabled
Output Disabled
Output Disabled
1
-
-
-
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Output Enabled
Default
1
1
1
1
1
1
1
1
IDT^TM PC MAIN CLOCK
14
1484B—01/21/10